Fault Tolerant Digital Data-Path Design via Control Feedback Loops

Boncalo, Oana; Amăricăi, Alexandru; Lendek, Zsófia

doi:10.3390/electronics9101721

Cited by 2 publications

(2 citation statements)

References 24 publications

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“…It was demonstrated through simulation that the suggested approach decreased hardware failure by utilizing TMR technique only when necessary. The researchers developed a new a feedback control loop connected to a digital pipeline hardware system with an appropriate dynamic model to lessen the impact of errors and faults effects on the output [15]. The digital blocks whose executed operation was rewinded were selected as data-path registers for the correction loops of a robotic industrial arm which have applied correction factors.…”

Section: Previous Workmentioning

confidence: 99%

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Khairullah,

Qassabbashi,

Kareem

2024

Bulletin EEI

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Safety-critical systems used in applications that demand high levels of dependability, efficiency, and fault-tolerance often use sequential logic circuits in its design and implementation. The safety-critical digital system typically uses latches, flip-flops, and other memory elements, which are prone to the effects of natural faults and single event upsets (SEUs) caused by radiation-induced effects. The faults can lead to subsystem failures due to the continuous advancement in the realization of the small size transistor. To design a reliable digital-based system, it is essential to develop new fault-tolerance approaches that are integrated into the design of sequential logic circuits. This work proposes a novel fault-tolerant approach based on the redundancy of sequential logic circuit, which consists of a variety of design components, D flip-flop storage elements linked to a fault injection unit, a duplicate modular redundancy, and data monitoring units with a switching circuit. The experimental simulation results using a five-state Markov chain analysis model prove that the proposed fault-tolerant system can achieve 0.99999998 for reliability of the fault detection coverage (C) which equal to 0.99999. Finally, we believe that using this new approach of fault-tolerance and redundancy would improve the dependability and reliability of next generation safety-critical applications.

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Section: Previous Workmentioning

confidence: 99%

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Khairullah,

Qassabbashi,

Kareem

2024

Bulletin EEI

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“…Control Feedback Loop Error Decimation (CFLED) is a revolutionary way for fault tolerance methodology for digital pipelined data-paths proposed in [8], which minimises the error magnitude at the outputs. From a control standpoint, the data-path is viewed as a process that is impacted by perturbations or defects.…”

Section: Related Workmentioning

confidence: 99%

Novel Double Modular Redundancy Based Fault-Tolerant FIR Filter for Image Denoising

Vaisakhi¹,

Surendran²

2023

Computer Systems Science and Engineering

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In signal processing and communication systems, digital filters are widely employed. In some circumstances, the reliability of those systems is crucial, necessitating the use of fault tolerant filter implementations. Many strategies have been presented throughout the years to achieve fault tolerance by utilising the structure and properties of the filters. As technology advances, more complicated systems with several filters become possible. Some of the filters in those complicated systems frequently function in parallel, for example, by applying the same filter to various input signals. Recently, a simple strategy for achieving fault tolerance that takes advantage of the availability of parallel filters was given. Many fault-tolerant ways that take advantage of the filter's structure and properties have been proposed throughout the years. The primary idea is to use structured authentication scan chains to study the internal states of finite impulse response (FIR) components in order to detect and recover the exact state of faulty modules through the state of non-faulty modules. Finally, a simple solution of Double modular redundancy (DMR) based fault tolerance was developed that takes advantage of the availability of parallel filters for image denoising. This approach is expanded in this short to display how parallel filters can be protected using error correction codes (ECCs) in which each filter is comparable to a bit in a standard ECC. "Advanced error recovery for parallel systems," the suggested technique, can find and eliminate hidden defects in FIR modules, and also restore the system from multiple failures impacting two FIR modules. From the implementation, Xilinx ISE 14.7 was found to have given significant error reduction capability in the fault calculations and reduction in the area which reduces the cost of implementation. Faults were introduced in all the outputs of the functional filters and found that the fault in every output is corrected.

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Fault Tolerant Digital Data-Path Design via Control Feedback Loops

Cited by 2 publications

References 24 publications

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Design and analysis of fault-tolerant sequential logic circuits for safety-critical applications

Novel Double Modular Redundancy Based Fault-Tolerant FIR Filter for Image Denoising

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