Fault-tolerant high performance scheme design

Abstract

Extending a set of faults on account of path delay ones (PDFs) for the fault-tolerant scheme previously oriented to transient or intermittent single stuck-at faults at gate poles of a synchronous sequential circuit is suggested. PDFs are also either transient or intermittent faults. The scheme is based on replicating a self-checking synchronous sequential circuit and using a checker for one of the circuit. We don't need to provide a self-testing property for the checker. It is supposed that each next fault appears when a previous one has disappeared. Estimations of the scheme complexity, and its modification oriented to masking only PDFs are discussed.978-1-4673-7776-8/15/$31.00 ©2015 IEEE

A Fault-tolerant Sequential Circuit Design for Stuck-at Faults and Path Delay Faults

“…The complexity of schemes and their subcircuits are estimated by the number of NOT gates and two inputs gates. Table 4 illustrates the area overhead reduction of the proposed scheme as compared to TMR scheme and scheme from [9]. Use the following notations:…”

“…In the paper [9] was suggested a fault-tolerant sequential circuit design also based on two self-checking circuits for soft Path Delay Faults (PDFs) of the circuit. It includes two self-checking circuits, one self-testing checker and more simple error-masking interface than one in [8].…”

“…In [10] a fault-tolerant scheme based on totally self-checking system with low overhead in comparison with architectures suggested in [9] is considered. In contrast with these schemes it has only one self-checking combinational circuit and another circuit is conventional one.…”