Fault tolerant methods for reliability in FPGAs

Stott, Edward; Sedcole, P.; Cheung, Peter Y. K.

doi:10.1109/fpl.2008.4629973

Cited by 64 publications

(30 citation statements)

References 49 publications

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“…These methods use different replications, at different granularities, to increase the system reliability [8]. In this regard, different fine and coarse grain redundancy-based FT techniques for spacecomputing systems have been investigated in [9], [10]. As an example of the application of FT techniques in FPGAs, a system-level Duplication With Compare (DWC) FT technique has been presented in [11] to improve the reliability of adaptive equalizers, implemented on FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Ramezani

Sedaghat

Clemente

2017

IEEE Trans. VLSI Syst.

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Abstract-This study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This technique, which has been named Task Early-fetch, can be applied to a sequence of one or several applications, represented as task graphs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous task graph, plus increasing the redundancy level of the early-fetched tasks. Experimental results on actual task graphs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant task graphs, and the improvement is more significant when applying to faulttolerant task graphs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at run-time and steers the execution of the running task graphs. It demonstrates that, with 0.03% consumption of FFs and LUTs and also 1.22% occupancy of BRAMs available on a Xilinx Virtex UltraScale XCVU095-2FFVA2104E FPGA, the required run-time computations can be carried out in negligible delays.

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Section: Related Workmentioning

confidence: 99%

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Ramezani

Sedaghat

Clemente

2017

IEEE Trans. VLSI Syst.

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“…Several studies have investigated fault tolerance in FPGAs [1], [3]. In this paper, we consider situations in which fault tolerance is required owing to physical faults falling into the following categories.…”

Section: Related Workmentioning

confidence: 99%

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Amagasaki

Nishitani

Inoue

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYFault tolerance is an important feature for the system LSIs used in reliability-critical systems. Although redundancy techniques are generally used to provide fault tolerance, these techniques have significantly hardware costs. However, FPGAs can easily provide high reliability due to their reconfiguration ability. Even if faults occur, the implemented circuit can perform correctly by reconfiguring to a fault-free region of the FPGA. In this paper, we examine an FPGA-IP core loaded in SoC and introduce a fault-tolerant technology based on fault detection and recovery as a CAD-level approach. To detect fault position, we add a route to the manufacturing test method proposed in earlier research and identify fault areas. Furthermore, we perform fault recovery at the logic tile and multiplexer levels using reconfiguration. The evaluation results for the FPGA-IP core loaded in the system LSI demonstrate that it was able to completely identify and avoid fault areas relative to the faults in the routing area.

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“…2. The red part of the cube shows the embedded SEDC 2 coding scheme in SEDC 3 . Note that when there is a 2-bit unidirectional change in data word '001' to '111' (two MSB's changing from '00' to '11'), the code is changing in the opposite direction (LSB of the code changes from '1' to '0').…”

Section: Scalable Error Detection Coding (Sedc) Algorithmmentioning

confidence: 99%

“…In faulttolerant reconfigurable systems, self-checking LUTs must detect all the unidirectional errors even when the system is functioning, that is, online fault detection. Online fault detection methods can be broadly classified as redundancy and error coding [3]. When using modular or time redundancy techniques there is an area overhead or latency overhead by two or three times [4].…”

Section: Introductionmentioning

confidence: 99%

Self-Checking Look-up Tables using Scalable Error Detection Coding (SEDC) Scheme

Lee¹,

Siddiqui

Somasundaram³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in faulttolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with selfchecking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3-and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for selfchecking than LUT with traditional Berger Coding scheme.

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Fault tolerant methods for reliability in FPGAs

Cited by 64 publications

References 49 publications

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core

Self-Checking Look-up Tables using Scalable Error Detection Coding (SEDC) Scheme

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