Fault tolerant quantum cellular array (QCA) design using triple modular redundancy with shifted operands

Wei, T.; Wu, K.; Karri, R.; Orailoglu, A.

doi:10.1109/aspdac.2005.1466555

Cited by 16 publications

(4 citation statements)

References 8 publications

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“…Thermodynamic stability was inspected with a statistical mechanical model in [25], and triple modular redundancy was proposed as a circuit improvement in [26]. The scaling properties of the QCA primitives have been inspected in [27,28], and fault simulations have been shown in [29,30].…”

Section: Reliabilitymentioning

confidence: 99%

Binary Adders on Quantum-Dot Cellular Automata

Hänninen

Takala

2008

J Sign Process Syst Sign Image Video Technol

117

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This article describes the design of adder units on quantum-dot cellular automata (QCA) nanotechnology, which promises very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells. We construct pipelined structures without the earlier noise problems, avoided by careful clocking organization, and the modular layouts are verified with the QCADesigner coherence vector simulation. Our designs occupy only a fraction of area compared to the previous noise rejecting design, while having also superior performance, and it is shown that the wiring overhead of the arithmetic circuits on QCA grows with square-law dependence on the operand word length. Power analysis at the fundamental Landauer's limit shows, that the operating frequencies will indeed be bound by the energy dissipated in information erasure: under irreversible operation, the clock rates of the adder units on molecular QCA are only tens of gigahertz, while the switching speed of the technology is in the terahertz regime.

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Section: Reliabilitymentioning

confidence: 99%

Binary Adders on Quantum-Dot Cellular Automata

Hänninen

Takala

2008

J Sign Process Syst Sign Image Video Technol

117

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“…1 00 00 11 11 0 1 00 00 11 11 00 00 11 11 00 00 11 11 00 00 11 11 00 00 11 11 00 00 11 11 0 0 1 1 0 0 1 1 00 00 11 11 00 00 11 11 00 00 11 11 0 Till today different tiles are recognised as the well known fault tolerant architecture in QCA [4] which can achieve only 66.67% fault tolerance. TMR (Triple Modular Redundancy), is also used fault tolerant technique in QCA where input lines of TMR are shared by all the copies [10]. A failure in the lines may simultaneously affect two or all copies of computations and results in a faulty output.…”

Section: Qca Basicsmentioning

confidence: 99%

Design of Fault Tolerant Universal Logic in QCA

Sen

Mukherjee

Nath

et al. 2014

2014 Fifth International Symposium on Electronic System Design

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Design paradigms of logic circuits with Quantum-dot Cellular Automata (QCA) have been extensively studied in the recent past. Unfortunately, due to the lack of mature fabrication support, QCA-based circuits often suffer from various types of manufacturing defects and variations, and therefore, are unreliable and error-prone. QCA-based Exclusive-OR (XOR) gates are frequently used in the construction of several computing subsystems such as adders, linear feedback shift registers, parity generators and checkers. However, none of the existing designs for QCA XOR gates have considered the issue of ensuring fault-tolerance. Simulation results also show that these designs can hardly tolerate any fault. We investigate the applicability of various existing fault-tolerant schemes such as triple modular redundancy (TMR), NAND multiplexing, and majority multiplexing in the context of practical realization of QCA XOR gate. Our investigations reveal that these techniques incur prohibitively large area and delay and hence, they are unsuitable for practical scenarios. We propose here realistic designs of QCA XOR gates (in terms of area and delay) with significantly high fault-tolerance against all types of cell misplacement defects such as cell omission, cell displacement, cell misalign-ment and extra/additional cell deposition. Furthermore, the absence of any crossing in the proposed designs facilitates low-cost fabrication of such systems.

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“…One of the first reliability studies proposed using block gates to obtain fault tolerance [5], and the runtime error behavior of a metal-dot technology shift-register, implemented in laboratory environment, was analyzed in [4] and revisited in [6]. Thermodynamic stability was inspected with a statistical mechanical model in [7], and triple modular redundancy with shifted operands was proposed as a circuit improvement in [8]. The scaling properties of the QCA primitives were inspected in [9], [10], and fault simulations shown in [11], [12].…”

Section: Related Workmentioning

confidence: 99%

Reliability of a QCA Array Multiplier

Hänninen

Takala

2008

2008 8th IEEE Conference on Nanotechnology

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Defects and faults of the future circuit technologies have to be taken into account early in the design of digital systems. To form practical design guidelines, we study the relationship between system reliability and component failure rates, in the case of a binary multiplier unit on quantumdot cellular automata nanotechnology. The analysis is based on a decomposition of probabilistic transfer matrices, a versatile framework for computing the conditional probability of system failure. Our results indicate that passive wiring dominates the reliability of arithmetic designs on the nanotechnology. I. INTRODUCTIONHigh defect rates in the manufacturing process and various dynamic faults occurring during the runtime operation determine the practicality of digital designs, implemented with the future circuit technologies: the primitive components function or fail with imperfect stochastic characteristics, instead of the traditional deterministic behavior. A component with non-zero failure rate affects the reliability of the complete system, but these relations are unknown for many important applications, making it difficult to aim the costly improvements to the target of most effect on the total reliability. Designers are tempted to adopt overkill solutions, with unjustifiable cost, possibly attacking the fault-tolerance on a wrong design level.This paper explores the reliability of binary multiplication, executed on a massively parallel array multiplier (AM) structure. We compare the contribution of the passive wiring and the active computing hardware in a layout level implementation, based on quantum-dot cellular automata (QCA) nanotechnology, which is one of the foremost candidates to replace transistor based digital technologies. The nanotechnology is expected to reach circuit densities and clock frequencies several decades higher than the technological peak of the complementary metal oxide semiconductor (CMOS) [1]. The concept was introduced in early 1990s, and has been demonstrated in with small proof-of-concept systems [2]- [4].Our analysis, based on the probabilistic transfer matrix (PTM) approach, shows that the total reliability of an array multiplier depends linearly on the failure rates of the macro components (passive wiring and active logic). The wire blocks dominate the total reliability, in comparison with the contribution of the actual computation logic (full adders and summand formation). The results are used in conjunction with the previous studies, to transform the architectural requirements into the failure rates of the low-level circuit primitives.The rest of this paper is organized as follows: Section II summarizes the previous research on QCA reliability, while

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Fault tolerant quantum cellular array (QCA) design using triple modular redundancy with shifted operands

Cited by 16 publications

References 8 publications

Binary Adders on Quantum-Dot Cellular Automata

Binary Adders on Quantum-Dot Cellular Automata

Design of Fault Tolerant Universal Logic in QCA

Reliability of a QCA Array Multiplier

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