Fault tolerant reconfigurable hardware design using BIST on SRAM: A review

Pundir, Aditya Kumar Singh; Sharma, Om P.

doi:10.1109/i2c2.2017.8321907

Cited by 7 publications

(2 citation statements)

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“…FPGAs are the perfect system to implement TMR due to its parallel design architecture. [382,383], Built-In Self Test (BIST) [344, [384][385][386][387][388], hash function implementations [389][390][391][392][393][394], parallel and high speed Cyclic Redundancy Check (CRC) implementations [395][396][397][398] and efficient intrusion detection systems [399][400][401][402][403][404].…”

Section: Computer Securitymentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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Field Programmable Gate Array (FPGA) is a general purpose programmable logic device that can be configured by a customer after manufacturing to perform from a simple logic gate operations to complex systems on chip or even artificial intelligence systems. Scientific publications related to FPGA started in 1992 and, up to now, we found more than 70,000 documents in the two leading scientific databases (Scopus and Clarivative Web of Science). These publications show the vast range of applications based on FPGAs, from the new mechanism that enables the magnetic suspension system for the kilogram redefinition, to the Mars rovers’ navigation systems. This paper reviews the top FPGAs’ applications by a scientometric analysis in ScientoPy, covering publications related to FPGAs from 1992 to 2018. Here we found the top 150 applications that we divided into the following categories: digital control, communication interfaces, networking, computer security, cryptography techniques, machine learning, digital signal processing, image and video processing, big data, computer algorithms and other applications. Also, we present an evolution and trend analysis of the related applications.

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Section: Computer Securitymentioning

confidence: 99%

Field Programmable Gate Array Applications—A Scientometric Review

2019

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“…Several other galloping bit/patterns-based algorithms were also developed to enhance the fault coverage of targeted fault classes [11,12]. The modified galloping pattern-based and checkerboard algorithms also provide good diagnosis speed and fault coverage [13][14][15][16][17][18]. In these designs, the MBISR hardware consists of three main modules i.e.…”

Section: Introductionmentioning

confidence: 99%

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

Pundir

2019

IET Circuits, Devices & Systems

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The article presents a new augmented and improved MMBISR for SRAM using hybrid redundancy analysis (HRA). The presented algorithm is the augmented version of essential spare pivoting (ESP) and local repair most (LRM). The algorithm proposes the best solution by providing optimised set of row and column combination which were suitable for the repairing process. In the proposed redundancy analysis (RA) algorithm, the fault dictionary can be updated or fixed concurrently, according to MBIST needs and supplied control signals. The row and column pivots and repair requests are also serviced according to precedency list prepared by the comparing actions. The comparative analysis with LRM and ESP-RA algorithms shows that the proposed algorithm has reduced complexity and tracing time in terms of implementation and in terms of finding row and column pivots. For the implementation, a MBISR hardware structure is designed and tested using suitable VHDL descriptions that were targeted for Virtex-5, xc5vlx30 FPGA. The results were also justified that the proposed algorithm is quite effective as the repair rate is increased up to 4% compared to the ESP. However, some nominal area penalty is observed as compared to ESP.

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