Fault-tolerant typed assembly language

Perry, Frances; Mackey, Lester; Reis, George A.; Ligatti, Jay; August, David I.; Walker, David

doi:10.1145/1250734.1250741

Cited by 25 publications

(22 citation statements)

References 27 publications

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“…Elsman [16] shows how to extend that calculus with simplified error detection operations. More recent work applies these abstract, high-level ideas directly to assembly langauge [17,18]. The main drawback of these type-based approaches is that each new fault tolerance scheme requires its own type system.…”

Section: Related Workmentioning

confidence: 99%

Faulty Logic: Reasoning about Fault Tolerant Programs

Meola

Walker

2010

Programming Languages and Systems

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Abstract. Transient faults are single-shot hardware errors caused by high energy particles from space, manufacturing defects, overheating, and other sources. Such faults can be devastating for security-and safetycritical systems. In order to mitigate these problems, software developers can add redundancy in various ways to their software systems. However, such redundancy is hard to reason about and corner cases are easy to miss, leaving these systems vulnerable. To solve this problem, we have developed a logic, based on Separation Logic, for reasoning about faults as resources. We show how to use this logic as a language of assertions and incorporate it into a Hoare Logic for verifying imperative programs. This Hoare Logic is parameterized by a formal fault model and it can be used to prove imperative programs correct with respect to that model. In addition to developing this basic verification platform, we have designed a modal operator that abstracts away the effects of individual faults, enabling modularization of proofs and greatly simplifying the reasoning involved. The logic is proved sound and studied through a number of examples, including a simplified version of the RSA Sign/Verify algorithm.

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Section: Related Workmentioning

confidence: 99%

Faulty Logic: Reasoning about Fault Tolerant Programs

Meola

Walker

2010

Programming Languages and Systems

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“…Oh et al Hybrid software checking systems are proposed to mitigate the high cost in pure software checking systems [47,54]. These systems use several special designed hardware structures that were originally proposed in hardware redundant multithreading schemes.…”

Section: Software-based Approachesmentioning

confidence: 99%

“…[68] reports that the leading thread dominates the SRMT execution time, so the save on trailing checks may not help the performance much. But the save on cross-core communication bandwidth is projected to be In the case of hybrid solutions [47,54], ESoftCheck reduces the number of hardware checks, and lowers register pressure.…”

Section: Benefit For Software-only and Hybrid Solutionsmentioning

confidence: 99%

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Efficient software checking for fault tolerance

Garzarán

Snir

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

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As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. Software checking approaches are attractive because they require little hardware modification and can be easily adjusted to fit different reliability and performance requirements. Unfortunately, software checking adds a significant performance overhead.In order to make software checking system more attractive, this dissertation proposes three optimization techniques that reduce the overhead of software error checking approaches. The first technique uses boolean logic to identify code patterns that correspond to outcome tolerant branches. We develop a compiler algorithm that finds those patterns and removes the unnecessary replicas. In the second technique we evaluate the performance benefit obtained by removing address checks before load and stores. In addition, we evaluate the overheads that can be removed when the register file is protected in hardware. The third technique ESoftCheck composes of a set of compiler optimizations to detect and remove "non-vital" checks. ESoftCheck optimizes redundant checks, checks before loop induction variables and invariants and unnecessary checks on platforms where registers are hardware-protected with parity or ECC. ESoftCheck also provides knobs to trade reliability for performance based on the support for recovery and the degree of trustiness of the operations.In the end, this dissertation proposes an interesing future work, which is to find ii a set of variables protecting which it can most likely catch harmful errors that would cause Silent Data Corruption to the program. By ignoring non-harmful errors, the cost spent on detecting them and unnecessary rollbacks can be saved.iii To my husband Yue Zhou and my parents.iv

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“…For multithreaded code [33], ESoftCheck also reduces the number of communication and synchronization instructions executed. In the case of hybrid solutions [27], [23], ESoftCheck reduces the number of hardware checks.…”

Section: Introductionmentioning

confidence: 99%

ESoftCheck: Removal of Non-vital Checks for Fault Tolerance

Garzarán

Snir

2009

2009 International Symposium on Code Generation and Optimization

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Abstract-As semiconductor technology scales into the deep submicron regime the occurrence of transient or soft errors will increase. This will require new approaches to error detection. Software checking approaches are attractive because they require little hardware modification and can be easily adjusted to fit different reliability and performance requirements. Unfortunately, software checking adds a significant performance overhead.In this paper we present ESoftCheck, a set of compiler optimization techniques to determine which are the vital checks, that is, the minimum number of checks that are necessary to detect an error and roll back to a correct program state. ESoftCheck identifies the vital checks on platforms where registers are hardware-protected with parity or ECC, when there are redundant checks and when checks appear in loops. ESoftCheck also provides knobs to trade reliability for performance based on the support for recovery and the degree of trustiness of the operations. Our experimental results on a Pentium 4 show that ESoftCheck can obtain 27.1% performance improvement without losing fault coverage.

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Fault-tolerant typed assembly language

Cited by 25 publications

References 27 publications

Faulty Logic: Reasoning about Fault Tolerant Programs

Faulty Logic: Reasoning about Fault Tolerant Programs

Efficient software checking for fault tolerance

ESoftCheck: Removal of Non-vital Checks for Fault Tolerance

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