FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

Abstract

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the areadelay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations; 2) diagonal direct links are incorporated to improve the flexibility of local communication; and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by 3.6× compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective areadelay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.

Fracturable DSP Block for Multi-context Reconfigurable Architectures

“…We also observe a P-D product reduction of 6.43% across the benchmark circuits over the NATURE architecture with fixed precision DSP block. We also compare the results of NATURE with the fracturable DSP block against the FDR 2.0 architecture [5] that incorporates a DSP block with 3 pipeline stages. Compared to the fixed precision DSP block available on the FDR architecture, the fracturable nature of our DSP block enables the mapping tool to merge more DSP operations on to the same DSP block.…”

An Efficient Method of Parallel Multiplication on a Single DSP Slice for Embedded FPGAs

“…In embedded computing systems, DSP (Digital Signal Processor) slices inside FPGAs (Field Programmable Gate Arrays), are well-known as one of the most precious and limited resources [1]- [3]. Designers always expect to use the limited DSP resource to accomplish as much work as possible in a given time [4]. For example, a DSP slice configured as multiplier can do a multi-digit multiplication in one clock cycle.…”