Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique

Sun, Lei; Li, D. Y.; Liu, X.Y.; Han, Ruqi

doi:10.1016/j.mejo.2005.05.012

Search citation statements

Order By: Relevance

Paper Sections

Select...

Introduction1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2006

2017

Publication Types

Select...

Article3

Relationship

Self Cite0

Independent3

Authors

Journals

Cited by 3 publications

(1 citation statement)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For example, the registration of separate masks demands high precision in nano-scale patterning. Recently, we have reported a method [9] to fabricate planar asymmetric SB-MOSFET devices (ASB), in which the complicated chemical mechanical polishing (CMP) process is involved.…”

Section: Introductionmentioning

confidence: 99%

A planar asymmetric Schottky barrier source/drain structure for nano-scale MOSFETs

Sun¹,

Li²,

Zhang³

et al. 2006

Semicond. Sci. Technol.

View full text Add to dashboard Cite

An n-channel planar asymmetric Schottky barrier source/drain MOSFET (ASB), in which the source-side Schottky barrier is higher (0.9 eV, for PtSi) and the drain-side one is lower (0.2 eV, for ErSi), has been investigated. A fabrication proposal for nano-scale ASB devices has been put forward based on the spacer technique. This method is compatible with conventional CMOS processing. The characteristics of a 28 nm gate-length ASB device have been simulated with a numerical simulator, and the data are compared with the simulated results of corresponding conventional Schottky barrier MOSFETs. Comparison results have demonstrated that the ASB structure can efficiently suppress the leakage current and the I on /I off ratio can be much improved.

show abstract

Section: Introductionmentioning

confidence: 99%