Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminum/TEOS Process

Heitzinger, Clemens; Sheikholeslami, A.; Badrieh, Fuad; Puchner, H.; Selberherr, S.

doi:10.1109/ted.2004.829868

Cited by 9 publications

(6 citation statements)

References 6 publications

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“…The first set consists of 45 cases for the deposition of silicon nitride with the following geometrical parameters D, H, and T (cf. The process conditions of the deposition of silicon nitride and silicon dioxide were the same as those investigated in [2] and [3], respectively. Therefore, the parameters extracted during those two investigations are also used by our new investigations.…”

Section: The Geometrical Parameters Of Investigationsmentioning

confidence: 99%

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Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers

Sheikholeslami

Parhami

Puchner

et al. 2007

J. Phys.: Conf. Ser.

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Final passivation planarization is achieved by optimizing the stack height and trench width for technologies that are sensitive to passivation planarization like image sensor processes. Deposition profiles obtained by using our topography simulator elsa (Enhanced Level Set Applications) predict a range of trench width, stack height, and the thickness of the deposited layers which lead to a sufficient planarization margin. Furthermore, these predictions enable design of trenches with a sufficient side wall and bottom coverage in order to guarantee a proper moisture seal.

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Section: The Geometrical Parameters Of Investigationsmentioning

confidence: 99%

“…The topography simulator elsa developed at our institute is based on a level set method [1] for tracking moving boundaries in two and three dimensions. elsa is capable of handling different deposition and etching models and has been proven for different semiconductor manufacturing processes [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers

Sheikholeslami

Parhami

Puchner

et al. 2007

J. Phys.: Conf. Ser.

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“…A representation of the surface as a set of overlapping disks is used to approximate a closed surface. Heitzinger et al showed a method to accelerate such Monte Carlo based flux calculations by coarsening the explicit surface mesh representing the surface [ 15 ]. Recently, Yu et al presented a 3D topography simulation of a deep reactive ion etching (DRIE) process [ 16 ].…”

Section: Introductionmentioning

confidence: 99%

Accelerating Flux Calculations Using Sparse Sampling

et al. 2018

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The ongoing miniaturization in electronics poses various challenges in the designing of modern devices and also in the development and optimization of the corresponding fabrication processes. Computer simulations offer a cost- and time-saving possibility to investigate and optimize these fabrication processes. However, modern device designs require complex three-dimensional shapes, which significantly increases the computational complexity. For instance, in high-resolution topography simulations of etching and deposition, the evaluation of the particle flux on the substrate surface has to be re-evaluated in each timestep. This re-evaluation dominates the overall runtime of a simulation. To overcome this bottleneck, we introduce a method to enhance the performance of the re-evaluation step by calculating the particle flux only on a subset of the surface elements. This subset is selected using an advanced multi-material iterative partitioning scheme, taking local flux differences as well as geometrical variations into account. We show the applicability of our approach using an etching simulation of a dielectric layer embedded in a multi-material stack. We obtain speedups ranging from 1.8 to 8.0, with surface deviations being below two grid cells (0.6–3% of the size of the etched feature) for all tested configurations, both underlining the feasibility of our approach.

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“…Our two-dimensional investigations have predicted very well the void profile for the calculation of capacitance contributing in RC timing delays stemming from metal lines in interconnect structures [1]. The parameters for calibration and optimization of simulation results with measurements were extracted by SIESTA (Simulation Environment for Semiconductor technology Analysis) [2].…”

Section: Introductionmentioning

confidence: 99%

Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines

Sheikholeslami

Parhami

Heinzl³

et al. 2005

2005 International Conference on Simulation of Semiconductor Processes and Devices

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We present an analysis of deposition of silicon nitride and silicon dioxide layers into three-dimensional interconnect structures. The investigations have been performed using our general purpose topography simulator ELSA (Enhanced Level Set Applications). We predict void formation and its characteristics, which play an important role for the formation of cracks which are observed during the passivation of layers covering IC chips.

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Feature-Scale Process Simulation and Accurate Capacitance Extraction for the Backend of a 100-nm Aluminum/TEOS Process

Cited by 9 publications

References 6 publications

Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers

Planarization of Silicon Dioxide and Silicon Nitride Passivation Layers

Accelerating Flux Calculations Using Sparse Sampling

Applications of Three-Dimensional Topography Simulation in the Design of Interconnect Lines

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