2012
DOI: 10.1007/s10703-011-0135-z
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Fences in weak memory models (extended version)

Abstract: We present a class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and by the visibility of inter-and intra-processor communications through memory (e.g. store atomicity relaxation). We prove results on the required behaviour and placement of memory fences to restore a given model (such as Sequential Consistency) from a weaker one. Based on this class of models we develop a tool, diy, that systematically and automatically generates and runs… Show more

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Cited by 30 publications
(56 citation statements)
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“…Verifiers for weak memory broadly come in two flavours: the "operational approach", in which buffers are modelled concretely [3,17,26,29,30], and the "axiomatic approach", in which the observable effects of buffers are modelled indirectly by (axiomatically) constraining the order of instruction executions [2,9,11,15]. The former often relies on interleaving semantics and employs transition systems as the underlying mathematical framework.…”
Section: Related Workmentioning
confidence: 99%
“…Verifiers for weak memory broadly come in two flavours: the "operational approach", in which buffers are modelled concretely [3,17,26,29,30], and the "axiomatic approach", in which the observable effects of buffers are modelled indirectly by (axiomatically) constraining the order of instruction executions [2,9,11,15]. The former often relies on interleaving semantics and employs transition systems as the underlying mathematical framework.…”
Section: Related Workmentioning
confidence: 99%
“…Namely, the read action in t [1] does not allow to read only the most recent value (10, n 1 ) when it takes place too early to allow the other replicas to synchronise and restore consistency.…”
Section: Propositionmentioning
confidence: 99%
“…Within this research thread, [18,19] focus on the correctness of x86 assembly code via verified compilers, [16] presents a proof system for x86 assembly code based on a rely-guarantee assertion method, [13] proposes an axiomatic model for POWER memory model, equivalent to the operational specification given in [17], and illustrates how it can be used for verification using a SAT constraint solver. A general account of weak memory models is given in [1], together with a mechanism of memory fences (i.e., barriers located in the code) that preserve properties such as sequential consistency, and an automatic generation of tests for processors implementations. Existing work on memory models also addresses higher levels of abstraction.…”
mentioning
confidence: 99%
“…Example 11 illustrates how one can guarantee strong consistency properties by introducing synchronisation actions in the processes. This approach is similar to applying memory fences (i.e., barriers located in the code) when using weak memory models [4]. Example 12 underlines that, instead, in some other scenarios strong consistency can be guaranteed by relaxing or adapting the notion of observation.…”
Section: Examplementioning
confidence: 99%
“…Within this research thread, [22,23] focus on the correctness of x86 assembly code via verified compilers, [20] presents a proof system for x86 assembly code based on a rely-guarantee assertion method, [17] proposes an axiomatic model for the memory model of POWER multiprocessors, equivalent to the operational specification given in [21], and illustrates how it can be used for verification using a SAT constraint solver. A general account of weak memory models is given in [4], together with a mechanism based on memory fences that preserve properties such as sequential consistency, and an automatic generation of tests for processors implementations. With respect to the work on hardware memory models, we consider a higher level of abstraction, focusing on consistency of replicated cloud stores.…”
Section: Related Workmentioning
confidence: 99%