Ferroelectric Field-Effect Transistor-Based 3-D NAND Architecture for Energy-Efficient on-Chip Training Accelerator

Abstract

Different from the deep neural network (DNN) inference process, the training process produces huge amount of intermediate data to compute the new weights of the network. Generally, on-chip global buffer (e.g. SRAM cache) has limited capacity because of its low memory density, therefore the off-chip DRAM access is inevitable during the training sequences. In this work, a novel ferroelectric field effect transistor (FeFET) based 3D NAND architecture for on-chip training accelerator is proposed. The reduced peripheral circuit overheads owing to the low operation voltage of FeFET device and ultra-high density of 3D NAND architecture enables storing and computing all the intermediate data on chip during the training process. We present a custom design of 108 Gb chip with 59.91 mm 2 area with 45 % array efficiency. The relevant data mapping schemes for weights/activations/errors that are compatible to the 3D NAND architecture are investigated. The training performance was explored while ResNet-18 model is trained on this architecture with ImageNet dataset by 8-bit precision. Thanks to the minimized off-chip memory access, 7.76 TOPS/W of energy efficiency was achieved for 8-bit on-chip training.

Ferroelectric HfO2-based synaptic devices: recent trends and prospects

“…However, extending the CTFbased design for intensive write training would be challenging due to the high programming voltage (>20 V), the slow write latency (>10 µs) and limited endurance characteristics (<10 5 cycles) of the FN-tunneling-based program and erase scheme. Consequently, the FeFET-based 3D NAND architecture was regarded as an attractive means to overcome these limitations for in situ training [74]. Owing to its ultra-high density, a 3D NAND-based design for energy-efficient DNN training was feasible with minimized DRAM access by fully storing the huge amount of intermediate data on-chip.…”

“…For the VMM operations within the FeFET-based 3D NAND, a BL input scheme is used (explained in section 4.2). The details of the data flow and VMM operations of each training process (feed forward, error calculation, weight gradient calculation, and weight update) in each WL group are discussed in more detail in [74]. Subsequently, evaluation of the energy efficiency was performed for each on-chip training step using the DNN + NeuroSim framework [22], as shown in figure 17.…”

Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks

“…Thus, the required number of memory arrays and chip size should be further increased for the implementation of complex NN models which contain multiple layers. One of the solutions for this issue can be the use of three-dimensional (3D) memory structures, which can stack the memory elements without increasing the area of the chip 17,18 . Alternatively, there are approaches using conventional memory devices such as NOR flash, NAND flash, and AND flash to implement NNs [19][20][21][22] .…”