Neuro-inspired deep learning algorithms have shown promising futures in artificial intelligence. Despite the remarkable progress in software-based neural networks, the traditional von-Neumann hardware architecture has suffered from limited energy efficiency while facing unprecedented large amounts of data. To meet the performance requirements of neuro-inspired computing, large-scale vector-matrix multiplication is preferred to be performed in situ, namely compute-in-memory. Non-volatile memory devices with different materials have been proposed for weight storage as synaptic devices. Among them, HfO 2 -based ferroelectric devices have attracted great attention because of their low energy consumption, good complementarymetal-oxide-semiconductor (CMOS) compatibility and multi-bit per cell potential. In this review, recent trends and prospects of the ferroelectric synaptic devices are surveyed. First, we present the three-terminal synaptic devices based on the ferroelectric field effect transistor (FeFET), and discuss the switching physics of the intermediate states, the back-end-of-line integration and the 3D NAND architecture design. Then, we introduce a hybrid precision synapse concept that leverages the volatile charges on the gate capacitor of the FeFET and the non-volatile polarization on the gate dielectric of the FeFET. Lastly, we review two-terminal synaptic devices using the ferroelectric tunnel junction (FTJ) and ferroelectric capacitor (FeCAP). The design margins of the crossbar array with FTJ and FeCAP analyzed.

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Accurate cell conductance tuning is critical to realizing multilevel resistive random access memory (RRAM)-based compute-in-memory inference engines. To tighten the distribution of the cells of each state, we developed a two-step write-verify scheme within a limited number of iterations, which was tested on a test vehicle based on HfO 2 RRAM array to realize 2 bits per cell. The conductance of the cells is gathered in the targeted range within 10 loops of set and reset processes for each step. Moreover, the read noise of the RRAM cells is statistically measured and its impact on the upper bound of analog-to-digital converter (ADC) resolution is predicted. The result shows that the intermediate state cells under relatively high read voltage (e.g. 0.2 V) are vulnerable to the read noise. Fortunately, the aggregated read noise along the column will not disturb the output of a 5 bit ADC that is required for a 128 × 128 array with 2 bits per cell.

To efficiently deploy machine learning applications to the edge, compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency. Instant-on inference is further enabled by emerging non-volatile memory technologies such as resistive random access memory (RRAM). This paper reviews the recent progresses of the RRAM based CIM accelerator design. First, the multilevel states RRAM characteristics are measured from a test vehicle to examine the key device properties for inference. Second, a benchmark is performed to study the scalability of the RRAM CIM inference engine and the feasibility towards monolithic 3D integration that stacks RRAM arrays on top of advanced logic process node. Third, grand challenges associated with in-situ training are presented. To support accurate and fast in-situ training and enable subsequent inference in an integrated platform, a hybrid precision synapse that combines RRAM with volatile memory (e.g. capacitor) is designed and evaluated at system-level. Prospects and future research needs are discussed.

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