Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine

Shim, Wonbo; Luo, Yandong; Seo, Jae-sun; Yu, Shimeng

doi:10.1109/ted.2020.2985013

Cited by 31 publications

(21 citation statements)

References 21 publications

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“…'Read-Disturb' in ReRAM refers to the perturbation of the conductive filament during the data reading phase resulting in an unintended change of the stored memory state [34]. Experimental works [35], [36] suggest that read-disturb is severe only when the READ voltage across the ReRAM cell is > 0.3 V. To avoid read-disturb, we designed the time-based SA such that it can sense R ef f correctly for an I READ ≤ 30 µA (I READ > 30 µA could have provided a better sensing margin, but would have made the SA susceptible to read-disturb). The time-based sensing circuit is essentially a voltage-to-time converter followed by a time-domain comparator (D-flip flop).…”

Section: B Sensing Methodologymentioning

confidence: 99%

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Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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To overcome the 'von Neumann bottleneck', methods to compute in memory are being researched in many emerging memory technologies including Resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistoraccessed ReRAM array during READ operation. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. While many methods have been proposed recently to implement Boolean logic in memory, the latency of in-memory adders implemented as a sequence of such Boolean operations is exorbitant (O(n)). Parallel-prefix adders use prefix computation to accelerate addition in conventional CMOS-based adders. By exploiting the parallel-friendly nature of the proposed majority gate and the regular structure of the memory array, it is demonstrated how parallel-prefix adders can be implemented in memory in O(log(n)) latency. The proposed in-memory addition technique incurs a latency of 4•log(n)+6 for n-bit addition and is energy-efficient due to absence of sneak-currents in 1Transistor-1Resistor configuration.

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Section: B Sensing Methodologymentioning

confidence: 99%

“…Depending on the effective resistance R ef f , the BL reaches a voltage (V BL ≈ I READ × R ef f ). Read-disturb phenomenon [34]- [36] imposes a constraint that voltage across cell must be ≤ 0.3 V during READ. Hence a common-drain stage is used to boost the BL voltage to a level suitable for the following stage.…”

Section: B Sensing Methodologymentioning

confidence: 99%

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Reuben

Pechmann

2021

IEEE Trans. VLSI Syst.

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“…Even if the cell conductance distribution has been tightened within the targeted range using write-verify scheme, the non-ideal stability of the RRAM cells could cause conductance drift over usage and time. We investigated two reliability characteristics of the RRAM cell that are most critical to DNN inference accuracy, namely the read disturb [31] and the retention at high temperature baking [32].…”

Section: B Read Disturb and Retentionmentioning

confidence: 99%

“…Generally the resistance decreases gradually and saturates when it approaches to the lower bound limit. We modeled the gradual resistance change of intermediate states cells under read stress with lateral filament growth model where the radius of the filament changes from 6.4 nm to 19nm for State 2 and from 12 nm to 19 nm [31].…”

Section: B Read Disturb and Retentionmentioning

confidence: 99%

RRAM for Compute-in-Memory: From Inference to Training

Shim

Peng

et al. 2021

IEEE Trans. Circuits Syst. I

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To efficiently deploy machine learning applications to the edge, compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency. Instant-on inference is further enabled by emerging non-volatile memory technologies such as resistive random access memory (RRAM). This paper reviews the recent progresses of the RRAM based CIM accelerator design. First, the multilevel states RRAM characteristics are measured from a test vehicle to examine the key device properties for inference. Second, a benchmark is performed to study the scalability of the RRAM CIM inference engine and the feasibility towards monolithic 3D integration that stacks RRAM arrays on top of advanced logic process node. Third, grand challenges associated with in-situ training are presented. To support accurate and fast in-situ training and enable subsequent inference in an integrated platform, a hybrid precision synapse that combines RRAM with volatile memory (e.g. capacitor) is designed and evaluated at system-level. Prospects and future research needs are discussed.

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“…For a CIM architecture running a practical edge-AI application, such as a neural network-based image recognition for autonomous vehicles, the aforementioned device-level nonidealities (e.g., device variations) and crossbar-level issues (e.g., IR drop) manifest as errors in vector-matrix multiplication, resulting in degraded accuracy. Hence, it is necessary to mitigate their impact [53], [54].…”

Section: Bit-cell Configurations and Crossbar-level Issuesmentioning

confidence: 99%

Low-Power Memristor-Based Computing for Edge-AI Applications

Singh

Diware

Gebregiorgis

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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With the rise of the Internet of Things (IoT), a huge market for so-called smart edge-devices is foreseen for millions of applications, like personalized healthcare and smart robotics. These devices have to bring smart computing directly where the data is generated, while coping with the limited energy budget. Conventional von-Neumann architecture fail to meet these requirements due to e.g., memory-processor data transfer bottleneck. Memristor-based computation-in-memory (CIM) has the potential to realize smart local computing for highly parallel data-dominated AI applications by exploiting the inherent properties of the architecture and the physical characteristics of the memristors. This paper provides a broad overview of CIM architecture highlighting its potential and unique properties in enabling smart local computing. Moreover, it discusses design considerations of such architectures including both crossbar array as well as peripheral circuits; special attention is given to analog-to-digital converter (ADC), as it is the most critical unit of analog-based CIM operation e.g., vector-matrix multiplication (VMM). Finally, the paper outlines the potential future directions for CIM-based edge smart computing.

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Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine

Cited by 31 publications

References 21 publications

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates

RRAM for Compute-in-Memory: From Inference to Training

Low-Power Memristor-Based Computing for Edge-AI Applications

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