Ferroelectric negative capacitance MOSFET: Capacitance tuning &amp;amp; antiferroelectric operation

Khan, Asif Islam; Yeung, Chun Wing; Hu, Chenming; Salahuddin, Sayeef

doi:10.1109/iedm.2011.6131532

Cited by 294 publications

(166 citation statements)

References 5 publications

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“…For T F E = 380 nm, on the other hand, |C F E | > C M OS in a certain range of Q G and so C G becomes negative in the range only. In this condition, NCFETs become unstable, resulting in the hysteresis behavior [17]. Such a trade-off between high performance and hysteresis agrees well with previous results [12] [17].…”

Section: Characteristics Of Ncfetsupporting

confidence: 91%

“…In this condition, NCFETs become unstable, resulting in the hysteresis behavior [17]. Such a trade-off between high performance and hysteresis agrees well with previous results [12] [17]. Since hysteresis behavior is not desirable, we consider only hysteresis-free NCFETs hereafter.…”

Section: Characteristics Of Ncfetsupporting

confidence: 86%

“…The dependences of NCFET performances on ferroelectric thickness (T F E ) have been studied extensively [12]- [16]. Khan et al [17] provided guidelines for parameters to develop low-power NCFETs. Since NCFETs are based on conventional MOSFETs, they may be vulnerable to shortchannel effects (SCEs).…”

Section: Introductionmentioning

confidence: 99%

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Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Seo

Lee

Shin

2017

IEEE Trans. Electron Devices

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Abstract-We investigate the performance of hysteresisfree short-channel negative-capacitance field-effect transistors (NCFETs) by combining quantum mechanical calculations with the Landau-Khalatnikov equation. When the subthreshold swing (SS) becomes smaller than 60 mV/dec, a negative value of draininduced barrier lowering (DIBL) is obtained. This behavior, drain-induced barrier rising (DIBR), causes negative differential resistance (NDR) in the output characteristics of NCFETs. We also examine the performance of an inverter composed of hysteresis-free NCFETs to assess the effects of DIBR at the circuit level. Contrary to our expectation, although hysteresisfree NCFETs are used, hysteresis behavior is observed in the transfer properties of the inverter. Furthermore, it is expected that the NCFET inverter with hysteresis behavior can be used as a Schmitt trigger inverter.Index Terms-Subthreshold swing, ferroelectric, negative capacitance FET, hysteresis behavior, drain-induced barrier lowering, Schmitt trigger inverter

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Section: Characteristics Of Ncfetsupporting

confidence: 91%

Section: Characteristics Of Ncfetsupporting

confidence: 86%

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Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Seo

Lee

Shin

2017

IEEE Trans. Electron Devices

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“…A ferroelectric capacitor (FE) in series with a dielectric capacitor (DE) of a proper value can be biased in the negative capacitance region, providing a larger capacitance than the constituent DE capacitor [11]. In order to have a non-hysteretic NCFET, the ferroelectric NC and DE capacitor should be well matched to provide a positive total capacitance in the whole range of the operation [12], [13] while the slope of the charge line is smaller than the negative slope of the FE polarization [14], [15]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation

Saeidi

Jazaeri

Bellando

et al. 2017

2017 47th European Solid-State Device Research Conference (ESSDERC)

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Abstract-This work experimentally demonstrates negative capacitance MOSFETs in hysteretic and non-hysteretic modes of operation. A PZT capacitor is externally connected to the gate of commercial nMOSFETs fabricated in 28nm CMOS technology to explore the negative capacitance effect. In hysteretic devices, subthreshold slope as steep as 10mV/dec is achieved in the region where the ferroelectric represents an S-shape polarization. In addition, a matching condition is achieved between a PZT capacitor and the gate capacitance of MOSFETs fabricated on SOI substrates. For the first time, we achieve a non-hysteretic switch configuration in our fabricated MOSFETs, suitable for analog and digital applications, for which a reduction in the subthreshold swing is obtained down to 20mV/dec.

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“…12,13 PZT was used and designed with simulations and experiments to obtain an enhancement in capacitance concomitant with NC in the crystalline ferroelectric-dielectric bilayer. [14][15][16] The possible lowering of the n-factor can be addressed by employing a new transport mechanism, such as TFETs with a BTBT mechanism.…”

mentioning

confidence: 99%

Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on

et al. 2014

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Using a ferroelectric PbZrTiO3 gate stack, the range of the steep subthreshold swing in tunnel field-effect transistors was extended by 3.5 orders of magnitude demonstrating an improvement in the swing (by approximately double the slope). The drain conductance (gd) shows only 16% enhancement with large V DS (∼−1.5V) indicates internal voltage amplification with ferroelectric negative capacitance effect beneficial to small lateral drain-source bias voltages (−0.1 V). The concept of coupling the ferroelectric polarization is proposed. The power consumption is also discussed in low-power applications of steep subthreshold slope devices.

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Ferroelectric negative capacitance MOSFET: Capacitance tuning & antiferroelectric operation

Cited by 294 publications

References 5 publications

Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Analysis of Drain-Induced Barrier Rising in Short-Channel Negative-Capacitance FETs and Its Applications

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation

Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on

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