Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on

Lee, M. H.; Wei, Yun-Jie; Lin, J.-C.; Chen, C.-W.; Tu, Wen‐Hua; Tang, M.

doi:10.1063/1.4898150

Cited by 49 publications

(33 citation statements)

References 11 publications

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“…Hence, a surge of research activity is underway that focuses on harnessing the NC effect to reduce the operating voltage in FETs. To date, the NC effect has been studied with ferroelectric materials integrated into silicon-based FETs, [5][6][7][8][9][10][11][12][13][14] in which one of the key challenges is the variable substrate/ channel capacitance that leads to a diminished sub-60 mV/ dec region in the device subthreshold behavior. 5 From Eq.…”

mentioning

confidence: 99%

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

McGuire

Cheng

Price

et al. 2016

Applied Physics Letters

115

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There is a rising interest in employing the negative capacitance (NC) effect to achieve sub-60 mV/ decade (below the thermal limit) switching in field-effect transistors (FETs). The NC effect, which is an effectual amplification of the applied gate potential, is realized by incorporating a ferroelectric material in series with a dielectric in the gate stack of a FET. One of the leading challenges to such NC-FETs is the variable substrate capacitance exhibited in 3D semiconductor channels (bulk, Fin, or nanowire) that minimizes the extent of sub-60 mV/decade switching. In this work, we demonstrate 2D NC-FETs that combine the NC effect with 2D MoS 2 channels to extend the steep switching behavior. Using the ferroelectric polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)), these 2D NC-FETs are fabricated by modification of top-gated 2D FETs through the integrated addition of P(VDF-TrFE) into the gate stack. The impact of including an interfacial metal between the ferroelectric and dielectric is studied and shown to be critical. These 2D NC-FETs exhibit a decrease in subthreshold swing from 113 mV/decade down to 11.7 mV/decade at room temperature with sub-60 mV/decade switching occurring over more than 4 decades of current. The P(VDF-TrFE) proves to be an unstable option for a device technology, yet the superb switching behavior observed herein opens the way for further exploration of nanomaterials for extremely lowvoltage NC-FETs. Published by AIP Publishing. [http://dx.

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mentioning

confidence: 99%

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

McGuire

Cheng

Price

et al. 2016

Applied Physics Letters

115

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“…For example, E z is estimated to be 4.38×10 6 V/cm and 3.56×10 6 V/cm for the NC-GAA-TFET and GAA-TFET, respectively. In short, a large electric field at the tunnel junction is expected to result in a large tunneling current and steep SS in TFET devices [13]. Next, some design guidelines for the NC-GAA-TFETs will be discussed.…”

Section: Working Principle Of Nc-gaa-tfetsmentioning

confidence: 99%

“…To improve I on , semiconductors with narrow band gaps, such as SiGe, Ge [9], GeSn [10], and III-V compounds [11], have been employed in source engineering and as high-k gate dielectrics [12]. Very recently, M. H. Lee et al used the ferroelectric (FE) gate dielectric PZT to increase I on of a TFET due to its NC effect; this device is known as the NC TFET [13]. Nonetheless, the transfer characteristics demonstrated hysteretic behavior.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Jiang

2016

IEEE Trans. Nanotechnology

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Abstract-A short-channel negative capacitance gate-all-around tunnel field-effect transistor (NC-GAA-TFET) with a ferroelectric gate stack is proposed. Device performance is investigated by integrating three-dimensional (3D) numerical simulation and the one-dimensional (1D) Landau-Khalatnikov equation. It is shown that the NC-GAA-TFET has a steeper subthreshold swing and higher on-state current compared to conventional GAA-TFETs, and demonstrates no hysteretic behavior. Relevant analytical models, including the electrostatic potential model and the shortest tunnel path length (lsp), are developed to explain the device's operating principles and design optimization issues. Results from the analytical electrostatic potential model agree well with those of the numerical simulation. Furthermore, the analytical calculation shows that gate controllability over the channel is enhanced and the lsp value is significantly reduced as the thickness of the ferroelectric dielectric increases, resulting in better device characteristics. These results demonstrate the tremendous potential of NC-GAA-TFETs in low-power applications.Index Terms-Negative capacitance, tunnel field-effect transistor, analytical model, ferroelectric dielectric, numerical simulation, subthreshold swing.

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“…Therefore, it causes gate stack aspect ratios more suitable for scaling. Although there have been reports on the design and fabrication of ferroelectric PbZrTiO 3 gate stack TFETs, [11][12][13] p-n-p-n SOI TFET with the Si:HfO 2 ferroelectric gate stack has not been reported yet.…”

mentioning

confidence: 99%

“…In order to improve on-state current of TFETs, several techniques have been adopted such as hetrostructures, 3 band-gap engineering, 5 low band-gap and high mobility materials, 6 multiple gate, 7 vertical direction tunneling, 8 extended source, 9 source-pocket doping (p-n-p-n) 10 and ferroelectric gate stack. [11][12][13] The integration 14 and scaling issues 15 are biggest challenges for further utilization of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO 3 ) and strontium bismuth tantalate (SrBi 2 Ta 2 O 9 ). Recently, the ferroelectric behaviour of HfO 2 -based thin films are known.…”

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confidence: 99%

A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

2016

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In this paper, a silicon–on–insulator (SOI) p–n–p–n tunneling field–effect transistor (TFET) with a silicon doped hafnium oxide (Si:HfO2) ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3) and strontium bismuth tantalate (SrBi2Ta2O9) provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS) is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement) at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current) at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

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Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on

Cited by 49 publications

References 11 publications

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

Sub-60 mV/decade switching in 2D negative capacitance field-effect transistors with integrated ferroelectric polymer

Investigation of Negative Capacitance Gate-all-around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

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