FFT Algorithms Evaluation on a Homogeneous Multi-processor System-on-Chip

Airoldi, Roberto; Garzia, Fabio; Nurmi, Jari

doi:10.1109/icppw.2010.20

Cited by 9 publications

(2 citation statements)

References 13 publications

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“…The system power management strategy consisted of switching off the clocks of inactive processors while data was being downloaded and switching off the clocks of idle data transfer and storage hardware while the processor was busy and without the need of continuous data supply. Besides WCDMA cell search and timing synchronisation, the study cases include FFT algorithms [20] and a generic OFDM system receiver [21] developed using plain C code and defined in a parametric way, hence adding or removing nodes from the architecture does not require re-writing the software from scratch. Moreover the study cases showed a high scalability of the algorithm mapping and a high parallelization efficiency.…”

Section: Ninesilica Architecturementioning

confidence: 99%

Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC

Airoldi

Ahonen

Garzia

et al. 2010

J Sign Process Syst

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The performance of the W-CDMA cell search algorithm can be significantly improved using homogeneous general purpose Multi-Processor System-on-Chip (MPSoC) architectures. The application also scales well, as the number of processing nodes increases, allowing practical accelerations to become close to the theoretical maximum. In this work we describe a template MPSoC architecture based on multiprocessor computational clusters, called Ninesilica. Each Ninesilica consist of nine processing nodes based on COFFEE RISC architecture. MPSoC inter-and intra-cluster communication are enabled using hierarchical Network-on-Chip with dedicated point to point and broadcast communication services for better performance. Proposed template has been used to instantiate complete systems with one and four Ninesilica clusters, resulting in MPSoCs with respectively 9 and 36 computational nodes. The MPSoCs have been physically prototyped on a FPGA device, and the W-CDMA cell search algorithm has been mapped on both MPSoC platforms. The four Ninesilica MPSoC can execute

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Section: Ninesilica Architecturementioning

confidence: 99%

Implementation of W-CDMA Cell Search on a Highly Parallel and Scalable MPSoC

Airoldi

Ahonen

Garzia

et al. 2010

J Sign Process Syst

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“…There are many kinds of algorithm pattern, such as Radix-2 FFT algorithm, Radix-4 FFT algorithm, Radix-8 FFT algorithm, Split-Radix FFT algorithm and so on [6] [12]. Radix-2 FFT algorithm is suitable for hardware implementation, and it is usually employed to process 2 npoint FFT operation.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of 1-D and 2-D Mixed Architecture FFT Processor in Heterogeneous Multi-core SoC based on FPGA

Zhang¹,

Huang²,

Song³

et al. 2014

IJCA

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A novel architecture FFT processor which can carry on 1-D FFT algorithm or 2-D FFT algorithm corresponding different size of FFT is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for the heterogeneous multi-core SoC on chip application. The mixed architecture FFT processor achieves balance between high processing speed and resources. Compared with a conventional 1-D FFT processor, this FFT processor is characterized by having smaller resources consumption; compared with a 2-D FFT processor which is mapped onto a long point FFT architecture, it has higher processing speed. It employs the Radix-2 DIT-FFT algorithm and fixed addressing structure. It takes two ways to hide time consumed on data-path, one is read-ahead operation of dual-port RAM to hide the delay introduced by 12-stages pipeline of butterfly-unit and Memory access delay; the other is Ping-Pong operation of 3 groups of RAM to conceal data transmitting time. It also adopt twiddle factor compression algorithm to reduce ROM space. It can carry out 2 n (n is from range of 5 to 14) single-precision floating-point FFT/IFFT directly. As a result, we have implemented the mixed architecture FFT processor based on FPGA, and successfully applied it into the heterogeneous multi-core SoC.

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