Fibre channel fabrics: evaluation and design

Cherkasova, Ludmila; Kotov, Vadim E.; Rokicki, Tomas

doi:10.1109/hicss.1996.495447

Cited by 51 publications

(34 citation statements)

References 7 publications

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“…The paper [19] attempting this point using Smart routing. Rather than break the buffer cycles by arbitrarily picking a root node and performing a search from that node, instead building an explicit buffer dependency graph and search it for cycles.…”

Section: Smart Routingmentioning

confidence: 99%

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Optimising Up/Down Routing By Minimal Paths

Arora¹,

Rajkumar²

2010

IJCA

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Section: Smart Routingmentioning

confidence: 99%

“…Several solutions have been proposed in order to improve the up*/down* routing scheme, such as the In-transit Buffer [5], the DFS methodology [9] , Adaptive-trail routing [15] , and Smart routing [19].…”

Section: Figure 1 Bfs Spanning Tree and Assignment Of Directions To Lmentioning

confidence: 99%

Optimising Up/Down Routing By Minimal Paths

Arora¹,

Rajkumar²

2010

IJCA

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“…Section III mentions several off-chip resilient routing algorithms, most of which use up*/down* [27] as a baseline and modify the structure of its directed graph to balance traffic and enhance performance [10,21,26]. The simplest approach, the baseline up*/down* introduced by Autonet [27] in 1991, has been implemented in many high performance interconnects, such as Myrinet, InfiniBand, and Advanced Switching.…”

Section: Are Off-chip Up*/down* Schemes Applicable On-chip?mentioning

confidence: 99%

“…Off chip networks, such as clusters and Networks-Of-Workstations, first tackled the reliability challenge of unconstrained faults. A number of resilient routing algorithms that can be applied to any irregular topology (i.e., a topology that survived after a number of random faults in network links) has been proposed in this domain, including up*/down* (introduced in Autonet) [27], segmentbased routing [23], FX routing [26], L-turn [21], and smartrouting [10]. During reconfiguration, the surviving topology is communicated to a central node, which runs the reconreliability performance area bounded faults early work [12,16], VCs [17,18,29] flooding [6,24] limited n/a n/a pattern constraints convex [9,31], L or T [9], polygons [20] limited n/a n/a unbounded faults off-chip routing [10,21,23 figuration algorithm in software.…”

Section: Related Workmentioning

confidence: 99%

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Aisopos

DeOrio

Peh

et al. 2011

2011 International Conference on Parallel Architectures and Compilation Techniques

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Abstract-Extreme transistor technology scaling is causing increasing concerns in device reliability: the expected lifetime of individual transistors in complex chips is quickly decreasing, and the problem is expected to worsen at future technology nodes. With complex designs increasingly relying on Networks-on-Chip (NoCs) for on-chip data transfers, a NoC must continue to operate even in the face of many transistor failures. Specifically, it must be able to reconfigure and reroute packets around faults to enable continued operation, i.e., generate new routing paths to replace the old ones upon a failure. In addition to these reliability requirements, NoCs must maintain low latency and high throughput at very low area budget.In this work, we propose a distributed reconfiguration solution named Ariadne, targeting large, aggressively scaled, unreliable NoCs. Ariadne utilizes up*/down* for fast routing at high bandwidth, and upon any number of concurrent network failures in any location, it reconfigures to discover new resilient paths to connect the surviving nodes. Experimental results show that Ariadne provides a 40%-140% latency improvement (when subject to 50 faults in a 64-node NoC) over other on-chip state-of-the-art fault tolerant solutions, while meeting the low area budget of on-chip routers with an overhead of just 1.97%.

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“…Other routing algorithms like Smart [2] and DFS [6] achieve better performance than up*/down*. Smart first computes all possible paths for every source-destination pair, building the channel dependence graph (CDG).…”

Section: Introductionmentioning

confidence: 99%

Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing

Flich

López

Malumbres

et al. 2000

Lecture Notes in Computer Science

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Abstract. In previous papers we proposed the ITB mechanism to improve the performance of up*/down* routing in irregular networks with source routing. With this mechanism, both minimal routing and a better use of network links are guaranteed, resulting on an overall network performance improvement. In this paper, we show that the ITB mechanism can be used with any source routing scheme in the COW environment. In particular, we apply ITBs to DFS and routing algorithms, which provide better routes than up*/down* routing. Results show that ITB strongly improves DFS and Smart throughput (by 63% and 23%, respectively, for 64-switch networks).

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Fibre channel fabrics: evaluation and design

Cited by 51 publications

References 7 publications

Optimising Up/Down Routing By Minimal Paths

Optimising Up/Down Routing By Minimal Paths

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing

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Fibre channel fabrics: evaluation and design

Cited by 51 publications

References 7 publications

Optimising Up*/Down* Routing By Minimal Paths

Optimising Up*/Down* Routing By Minimal Paths

ARIADNE: Agnostic Reconfiguration in a Disconnected Network Environment

Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing

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Product

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Optimising Up/Down Routing By Minimal Paths

Optimising Up/Down Routing By Minimal Paths