Field programmable gate arrays and floating point arithmetic

Fagin, Barry; Renard, C.

doi:10.1109/92.311646

Cited by 54 publications

(21 citation statements)

References 2 publications

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“…Thus, the Double Precision Floating Point multiplier is implemented in Xilinx 12.4 and targeted on Vertex-4 FPGA [6]. The design is then tested and verified with a counter in chipscope analyzer.…”

Section: Ixconclusionmentioning

confidence: 99%

Implementation of Double Precision Floating Point Multiplier on FPGA

Keerthi¹,

K.V.Koteswararao²

2014

IJAREEIE

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ABSTRACT:Multiplication is one of the common arithmetic operations in Digital Signal Processing(DSP) computations. The proposed design is an implementation of an IEEE-754 Double Precision Floating Point Multiplier, which is better when compared to a single precision multiplier[1] because of its wider dynamic ranges and accuracy. A Double Precision Multiplier is designed using Xilinx 12.4 ISE tool and the design verification was done on Xilinx Vertex-4 ML403 platform which handles overflow, underflow cases and Truncation mode. A Comprehensive simulation and analysis of multiplier output is done using Xilinx ISim simulator and a test bench is written to generate an input stimulus.

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Section: Ixconclusionmentioning

confidence: 99%

Implementation of Double Precision Floating Point Multiplier on FPGA

Keerthi¹,

K.V.Koteswararao²

2014

IJAREEIE

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“…0.750 * 2 = 1.500 = 1 + 0.500 => b-2 = 1 0.500 * 2 = 1.000 = 1 + 0.000 => b-2 = 1 Fraction = 0.000 i.e. terminated We can say that the (0.375) 10 will be accurately converted into binary as (0.011) 2 . Not all decimal fraction will be described in a very finite digit binary fraction as an example we take 0.1 cannot be describe in precisely binary form [8].…”

Section: Conversion Binary To Floating Pointmentioning

confidence: 99%

“…Floating point number is the way to represent the real number into binary form, the IEEE 754 is the standard way to represents two different floating point font like binary interchange format and decimal interchange format [9]. For DSP application multimode floating point representation is required because the DSP applications involves large dynamic range.…”

Section: Floating Point Single Precision Multipliermentioning

confidence: 99%

“…If the value of exponent is greater than 0 and less than 255, and MSB is 1, then the number is said to be normalized number, and the real number is represented by 1. When we multiply two floating point format, 1-added to the exponent of the number then subtracting the bias from their result, 2-multiplying the significant of the numbers, and 3-calculating the sign by XORing the sign of the two numbers [10]. …”

Section: Floating Point Single Precision Multipliermentioning

confidence: 99%

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Design and Analysis of Multimode Single Precision Floating Point Arithmetic Unit Using Verilog

saraswat

Malik²

2017

ijsrm

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Abstract-This Paper Presents a Design and Analysis of Multimode Single Precision Floating PointArithmetic Unit Using VERILOG Hardware Description Language on FPGA. The multimode floating point arithmetic unit have addition, subtraction, multiplication and division operations. The device used is Zed Board Zynq Evaluation and Developed Kit (xc7z020clg484-1) on which the proposed design will be physically verified. We design and analyse the efficient multimode floating point arithmetic unit for IEEE 754 floating point number system, which gives a better implementation in terms of area of hardware. We have four separate units for four different arithmetic operations, by combining addition and subtraction unit into one and multiplication and division unit into one and by efficient optimization. The result of this combination is to reduce the number of LUTs used in FPGA. Thus the total area of hardware required will be reduced. The LUTs reduction is 14% and area reduction is 19%.

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“…Moreover, these efforts demonstrate that such customized formats enable significant speedups for certain chosen applications. The earliest work on IEEE floating-point [7] focused on single precision although found to be feasible but it was extremely slow. Eventually, it was demonstrated [8] that while FPGAs were uncompetitive with CPUs in terms of peak FLOPs, they could provide competitive sustained floating-point performance.…”

Section: Introductionmentioning

confidence: 99%

Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB

Grover¹,

Soni²

2014

IJIEEB

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-Most of the algorithms implemented in FPGAs used to be fixed-point. Floating-point operations are useful for computations involving large dynamic range, but they require significantly more resources than integer operations. With the current trends in system requirements and available FPGAs, floating-point implementations are becoming more common and designers are increasingly taking advantage of FPGAs as a platform for floating-point implementations. The rapid advance in Field-Programmable Gate Array (FPGA) technology makes such devices increasingly attractive for implementing floating-point arithmetic. Compared to Application Specific Integrated Circuits, FPGAs offer reduced development time and costs. Moreover, their flexibility enables field upgrade and adaptation of hardware to run-time conditions. A 32 bit floating point arithmetic unit with IEEE 754 Standard has been designed using VHDL code and all operations of addition, subtraction, multiplication and division are tested on Xilinx. Thereafter, Simulink model in MAT lab has been created for verification of VHDL code of that Floating Point Arithmetic Unit in Modelsim.

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Field programmable gate arrays and floating point arithmetic

Cited by 54 publications

References 2 publications

Implementation of Double Precision Floating Point Multiplier on FPGA

Implementation of Double Precision Floating Point Multiplier on FPGA

Design and Analysis of Multimode Single Precision Floating Point Arithmetic Unit Using Verilog

Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code using MATLAB

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