Figures of merit to characterize the importance of on-chip inductance

Ismail, Yehea; Friedman, Eby G.; Neves, J.L.

doi:10.1145/277044.277193

Cited by 103 publications

(54 citation statements)

References 12 publications

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“…where L is the unit inductance, R the unit resistance, and t r is the input signal transition time (Ismail, Friedman and Neves 1999;Ismail and Friedman 2000a).…”

Section: Preliminariesmentioning

confidence: 99%

Reducing inductive coupling variance in wide global signal busses

Soudan

2009

International Journal of Electronics

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As VLSI technology progresses deeper into the nanometer range, parasitic onchip inductance is becoming a major concern for functionality and performance. Most prominently affected are global signal busses comprised of a large number of nets and traversing long distances. In this work, we study the use of swizzling to reduce the variance in the strength of inductive coupling amongst different wires within a wide global signal bus to reduce the resulting variance in signal transition speed. The article presents a formulation of the swizzling technique and results to show that this technique significantly reduces inductive coupling variance within a wide global signal bus with zero area and routing resource penalty.

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“…where L is the unit inductance, R the unit resistance, and t r is the input signal transition time (Ismail, Friedman and Neves 1999;Ismail and Friedman 2000a).…”

Section: Preliminariesmentioning

confidence: 99%

Reducing inductive coupling variance in wide global signal busses

Soudan

2009

International Journal of Electronics

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“…Both metal-3 planes and metal-3 to metal-1 with 50% coverage as underlying layers are tested. The inductive effects on these long but narrow interconnects are still dominated by the line resistive behavior [10].…”

Section: A Bus Architecturementioning

confidence: 99%

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling

Zhang

Wilson

Bashirullah

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

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A 16-bit on-chip bus with driver pre-emphasis fabricated in 0.25μm CMOS technology attains an aggregate signaling data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional singleended voltage-mode static bus. The proposed bus is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

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“…The performance parameters such as crosstalk noise, propagation delay and power dissipation of a high-density high-speed chip are largely dependent on chip interconnects (Chandel, Sarkar, & Agarwal, 2005a;Kaushik & Sarkar, 2008;Kaushik, Sarkar, Agarwal, & Joshi, 2007). In current technology, the use of low resistance material, faster signal rise time, longer wire length and high switching speed leads to significant value of wire inductance (Ismail & Friedman, 1999). It is more effective to model the interconnect as distributed RLC transmission line rather than single RC (Deutsch et al, 1997).…”

Section: Introductionmentioning

confidence: 99%

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

Sharma¹,

Kaushik

Sharma

2013

International Journal of Electronics

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This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/ topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.

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Figures of merit to characterize the importance of on-chip inductance

Cited by 103 publications

References 12 publications

Reducing inductive coupling variance in wide global signal busses

Reducing inductive coupling variance in wide global signal busses

A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

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