Finding a Needle in the Haystack of Hardened Interconnect Patterns

Nikolić, Stefan; Zgheib, Grace; Ienne, Paolo

doi:10.1109/fpl.2019.00015

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Ilp Formulation Tightening1

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2022

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“…In principle this degree-matching approach could be recursively extended to counting the covered fanins/fanouts of predecessors and successors up to a certain distance [25], to further constrain the set of valid positions in the continuous relaxation. We have not tried this in practice yet.…”

Section: Ilp Formulation Tighteningmentioning

confidence: 99%

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Nikolić

Zgheib

Ienne

2022

ACM Trans. Reconfigurable Technol. Syst.

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In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer which moves a carefully selected subset of LUTs from their original positions, so that connections of the user circuit can be appropriately aligned with the direct connections of the FPGA, reducing the circuit’s critical path delay. We discuss various aspects of making such an approach practicable, from efficient formulation of the integer programs themselves, to appropriate selection of the movable nodes. These careful considerations enable simultaneous movement of tens of LUTs with tens of candidate positions each, in a matter of minutes. In this manner, the impact of additional connections on the critical path delay more than doubles, compared to the previously reported results that relied solely on architecture-oblivious placement.

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Section: Ilp Formulation Tighteningmentioning

confidence: 99%