Finding and Finessing Static Islands in Dynamically Scheduled Circuits

Cheng, Jianyi; Wickerson, John; Constantinides, George A.

doi:10.1145/3490422.3502362

Cited by 6 publications

(2 citation statements)

References 34 publications

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“…Cheng et al extended Dynamatic with the DASS methodology (Dynamic and Static Scheduling) [10], [18], which identifies static islands in an otherwise dynamically scheduled circuit. This improves the resource usage of the final circuits but the critical path stays often the same.…”

Section: B Combining Static and Dynamic Schedulingmentioning

confidence: 99%

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Szafarczyk,

Nabi,

Vanderbauwhede

2023

2023 International Conference on Field Programmable Technology (ICFPT)

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Dynamically scheduled high-level synthesis (HLS) achieves a higher throughput on codes with unpredictable memory accesses compared to statically scheduled HLS. However, the increased throughput comes at the price of increased resource usage and critical path length, resulting in lower clock frequency. The decrease in clock frequency can be significant, often nullifying any throughput improvements over static scheduling. Recent work presented methods for combining static and dynamic scheduling to achieve high throughput circuits with a fast critical path for dynamic codes. However, circuits that require dynamically scheduled memory still suffer from a decreased frequency. This paper fills this gap by presenting a method for achieving dynamically scheduled memory operations in HLS with a high frequency. Dynamic scheduling of memory operations is realized with a load-store queue (LSQ). We present a novel LSQ design adapted to the nature of spatial architectures with aggressive specialization to the target code -a unique opportunity in HLS. Our LSQ design works for both on-chip and off-chip memory and is integrated with a compiler that combines dynamic and static scheduling. We show a method to speculatively allocate addresses to our LSQ, significantly increasing pipeline parallelism in codes that could not benefit from an LSQ before. In stark contrast to traditional load value speculation, our approach adds no overhead on misspeculation. On a set of ten benchmarks, we show that our approach can achieve an up to 10× speedup on average against static HLS, and an up to 4× speedup against dynamic HLS that uses an LSQ from previous work, while also using several times fewer resources and scaling to larger queues.

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Section: B Combining Static and Dynamic Schedulingmentioning

confidence: 99%

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Szafarczyk,

Nabi,

Vanderbauwhede

2023

2023 International Conference on Field Programmable Technology (ICFPT)

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“…The key idea is to take a dynamically scheduled circuit as the starting point, and then to identify regions of the circuit that can be statically scheduled. These regions, which we call static islands [9], often consist of components with fixed or almost-fixed latency, and so benefit little from dynamic scheduling. Each static island is synthesized independently, and a wrapper is placed around it so that it can interface with its dynamically scheduled surroundings.…”

Section: Introductionmentioning

confidence: 99%

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets

Cheng

Fraca

Wickerson

et al. 2023

IEEE Trans. Comput.

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High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++, into a low-level hardware description. A key challenge in HLS is scheduling, i.e. determining the start time of all the operations in the untimed program. A major shortcoming of existing approaches to scheduling -whether they are static (start times determined at compile-time), dynamic (start times determined at run-time), or a hybrid of both -is that the static analysis cannot efficiently explore the run-time hardware behaviours. Existing approaches either assume the timing behaviour in extreme cases, which can cause sub-optimal performance or larger area, or use simulation-based approaches, which take a long time to explore enough program traces. In this article, we propose an efficient approach using probabilistic analysis for HLS tools to efficiently explore the timing behaviour of scheduled hardware. We capture the performance of the hardware using Timed Continous Petri nets with immediate transitions, allowing us to leverage efficient Petri net analysis tools for making HLS decisions. We demonstrate the utility of our approach by using it to automatically estimate the hardware throughput for balancing the throughput for statically scheduled components (also known as static islands) computing in a dynamically scheduled circuit. Over a set of benchmarks, we show that our approach on average incurs a 2% overhead in area-delay product compared to optimal designs by exhaustive search.

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Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis

Szafarczyk,

Nabi,

Vanderbauwhede

2023

2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)

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Finding and Finessing Static Islands in Dynamically Scheduled Circuits

Cited by 6 publications

References 34 publications

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets

Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis

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