Finding optimal L1 cache configuration for embedded systems

Janapsatya, Andhi; Ignjatović, Aleksandar; Parameswaran, Sri

doi:10.1145/1118299.1118482

Cited by 42 publications

(40 citation statements)

References 22 publications

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“…al argue that for embedded systems that are designed to run a single application the cache shall be optimized, with respect for energy consumption, for this application [7]. In their cache simulation tool they simultaneous evaluate different cache configurations.…”

Section: B Cache Evaluationmentioning

confidence: 99%

Design Space Exploration of Object Caches with Cross-Profiling

Schoeberl

Binder

Villazón

2011

2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing

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Abstract-To avoid data cache trashing between heapallocated data and other data areas, a distinct object cache has been proposed for embedded real-time Java processors. This object cache uses high associativity in order to statically track different object pointers for worst-case execution-time analysis. However, before implementing such an object cache, an empirical analysis of different organization forms is needed. We use a cross-profiling technique based on aspect-oriented programming in order to evaluate different object cache organizations with standard Java benchmarks. From the evaluation we conclude that field access exhibits some temporal locality, but almost no spatial locality. Therefore, filling long cache lines on a miss just introduces a high miss penalty without increasing the hit rate enough to make up for the increased miss penalty. For an object cache, it is more efficient to fill individual words within the cache line on a miss.

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Section: B Cache Evaluationmentioning

confidence: 99%

Design Space Exploration of Object Caches with Cross-Profiling

Schoeberl

Binder

Villazón

2011

2011 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing

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“…The experiment starts with trace generation using Tensilica Instruction Set Simulator [22]. The traces are then simulated for various cache configurations using our in-house cache simulator [21] (cache simulator tool was verified against DineroIV [23]). System definition provide the cache configurations and the HitME buffer configurations.…”

Section: Methodsmentioning

confidence: 99%

HitME: Low power Hit MEmory buffer for embedded systems

Janapsatya

Parameswaran

Ignjatovic

2009

2009 Asia and South Pacific Design Automation Conference

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In this paper, we present a novel HitME (Hit-MEmory) buffer to reduce the energy consumption of memory hierarchy in embedded processors. The HitME buffer is a small direct-mapped cache memory that is added as additional memory into existing cache memory hierarchies. The HitME buffer is loaded only when there is a hit on L1 cache. Otherwise, L1 cache is updated from the memory and the processor's memory request is served directly from the L1 cache. The strategy works due to the fact that 90% of memory accesses are only accessed once, and these often pollute the cache. Energy reduction is achieved by reducing the number of accesses to the L1 cache memory. Experimental results show that the use of HitME buffer will reduce the L1 cache accesses resulting in a reduction in the energy consumption of the memory hierarchy. This decrease in L1 cache accesses reduces the cache system energy consumption by an average of 60.9% when compared to traditional L1 cache memory architecture and an energy reduction of 6.4% when compared to filter cache architecture for 70nm cache technology.

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“…Simulation techniques provide an alternative to the static analyses, but are either restricted to in-order processors [9]- [11] or to the simulation of only one cache configuration at a time, thus resulting in an unacceptable execution time [12].…”

Section: Introductionmentioning

confidence: 99%

Fast and Precise Cache Performance Estimation for Out-Of-Order Execution

Douma

Altmeyer

Pimentel

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Design space exploration (DSE) is a key ingredient of system-level design, enabling designers to quickly prune the set of possible designs and determine, e.g., the number of the processing cores, the mapping of application tasks to cores, and the core configuration such as the cache organization. High-level performance estimation is a principle component of any systemlevel DSE: it has to be fast and sufficiently precise. Modern out-oforder architectures with caches pose a significant problem to this performance estimation process, as no simple one-to-one mapping of the number of cache misses and resulting cycle time exists. We present a high-level cache performance-estimation framework for out-of-order processors. Evaluation shows that our prediction method is on average 15 times faster than cycleaccurate simulation, while our estimates only show an average error of below 3.5%, reduce the pessimism of a naive highlevel performance estimation by around 66%, and still maintain a high fidelity. Our approach thus enables quick yet accurate performance estimation and extends the applicability of systemlevel DSE to out-of-order processors with caches.

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Finding optimal L1 cache configuration for embedded systems

Cited by 42 publications

References 22 publications

Design Space Exploration of Object Caches with Cross-Profiling

Design Space Exploration of Object Caches with Cross-Profiling

HitME: Low power Hit MEmory buffer for embedded systems

Fast and Precise Cache Performance Estimation for Out-Of-Order Execution

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