Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

Abstract

Abstract-One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement from a flattened design that no longer contains any high-level information related to the original design hierarchy. Unfortunately, placement is an NP-hard problem and as the size and complexity of designs implemented on FPGAs increases, SA does not scale well to find good solutions in a timely fashion. As modern FPGAs can be used to implement Systems-and Networks-on-Chip, designers are required to spend an increasing amount of time waiting for place and route tools to complete that is not being matched by an increase in the power of computing work stations.In this paper, we investigate if system-level information can be reconstructed from a flattened netlist and evaluate how that information is realized in terms of its locality in the final placement. If there is a strong relationship between good quality placements and system-level information, then it may be possible to divide a large design into smaller components and improve the time needed to create a good quality placement. Our preliminary results suggest that the locality property of the information embedded in the system-level HDL structure (i.e. "module", "always", and "if" statements) is greatly affected by both the designer and the design itself. A reconstructive algorithm, called affinity propagation, is also considered as a possible method of generating a meaningful coarse grain picture of the design.

Using data-mining techniques to improve combinatorial optimization algorithms

“…Applying data-mining to algorithmic results, as described above, provides us with a set of gems. Gems are clusters within the initial digital design that we could not find using upfront clustering techniques with theoretical relationships on the design netlists, 23 but by finding gems, which are localized placement knowledge extracted from repeated runs of the placement algorithm, we can do two things. First, we can use these gems as medium-grain blocks mixed with the unclustered blocks (fine-grain blocks) of the original design to examine new algorithms for placing this distribution of blocks.…”

Supergenes in a genetic algorithm for heterogeneous FPGA placement

“…Medium-grained structures are small collections of clusters (between 2 and 10) that are known to be strongly related to one another and should be placed in close proximity to each other on the FPGA. Our terminology for these medium-grained structures is super-clusters [33], which relates to our choice of using the term supergenes. Medium-grained placement would be no different than fine-grain placement if we could completely partition the entire design into the same sized super-clusters that could be placed in grid-like manner, but our research has found that there is only a small percentage of fine-grain clusters that can be organized into super-clusters and these super-clusters can vary in size (how many clusters are included in each).…”

“…Our preliminary work [33] describes clustering methods that can find these medium-grained structures during the CAD flow. However, our current findings suggest that these methods do not find high quality superclusters.…”