Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Abstract

A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

Variation-aware approaches with power improvement in digital circuits

“…In [35][36][37], some approaches are proposed for transistor sizing considering delay constraints with the least power consumption. Two methods are presented to reduce power in [38].…”

Power Consumption in CMOS Circuits

“…By this means, dynamic effective capacitance C dyn could be reduced when gates are downsized. By selectively downsizing the gates of a circuit, Aizik and Kolodny [18] demonstrated that dynamic and leakage energy dissipations can be reduced. Doing so, however, may lead to an increase in speed delay.…”