Eo ABSTRACTModern VLSI design requires a tradeoff between circuit speed and power dissipation. Timing optimization methods typically lead to excessive power consumption. In this work, we explore the energy/performance design space in CMOS circuits, to find gate sizes which produce the lowest possible power for any specified circuit delay. The tradeoff between energy and performance is achieved by relaxing the timing of the circuit through downsizing of the cells, thus reducing the active energy dissipation. Our analysis method is based on the commonly used logical effort methodology, extended to model power as well as delay. We introduce the energy/delay gain (EDG) notation, which measures the energy reduction rate that is achievable for each delay increase that is acceptable by the designer, and the local EDG (LEDG) property, as a metric for choosing an operating point on the EDG curve, while avoiding excessively low marginal costs. The proposed analytical method is shown to be accurate when compared to simulation based numerical optimization, and orders of magnitude faster.

No abstract

A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

No abstract

No abstract