Finding the right level of abstraction for minimizing operational expenditure

Mencer, Oskar; Vynckier, Erik; Spooner, James; Girdlestone, Stephen; Charlesworth, Oliver

doi:10.1145/2088256.2088262

Cited by 6 publications

(2 citation statements)

References 20 publications

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“…Field programmable gate arrays (FP-GAs) are particularly promising as an acceleration technology, as they can offer performance and energy improvements for a wide class of applications while also providing the reprogrammability and flexibility of software. Applications which exhibit large degrees of spatial and temporal locality and which contain relatively small amounts of control flow, such as those in the image processing [21,6], financial analytics [29,16,48], and scientific computing domains [42,1,11,50], can especially benefit from hardware acceleration with FPGAs. FPGAs have also recently been used to accelerate personal assistant systems [23] and machine learning algorithms like deep belief networks [31,32].…”

Section: Introductionmentioning

confidence: 99%

Generating Configurable Hardware from Parallel Patterns

Prabhakar

Koeplinger

Brown

et al. 2016

SIGOPS Oper. Syst. Rev.

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In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising as they offer significant performance and energy improvements compared to CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software development languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient.Functional languages with parallel patterns are a better fit for hardware generation because they both provide high-level abstractions to programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages. In this paper, we identify two optimizations that are important when using parallel patterns to generate hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 40× on a set of benchmarks from the data analytics domain.

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Section: Introductionmentioning

confidence: 99%

Generating Configurable Hardware from Parallel Patterns

Prabhakar

Koeplinger

Brown

et al. 2016

SIGOPS Oper. Syst. Rev.

View full text Add to dashboard Cite

show abstract

“…Field programmable gate arrays (FPGAs) are particularly promising as an acceleration technology, as they can offer performance and energy improvements for a wide class of applications while also providing the reprogrammability and flexibility of software. Applications which exhibit large degrees of spatial and temporal locality and which contain relatively small amounts of control flow, such as those in the image processing [22,7], financial analytics [31,17,53], and scientific computing domains [45,2,12,55], can especially benefit from hardware acceleration with FPGAs. FPGAs have also recently been used to accelerate personal assistant systems [24] and machine learning algorithms like deep belief networks [33,34].…”

Section: Introductionmentioning

confidence: 99%

Generating Configurable Hardware from Parallel Patterns

Prabhakar

Koeplinger

Brown

et al. 2016

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and energy improvements over CPUs for a wide class of applications and are far more flexible than fixed-function ASICs. However, FPGAs are difficult to program. Traditional programming models for reconfigurable logic use low-level hardware description languages like Verilog and VHDL, which have none of the productivity features of modern software languages but produce very efficient designs, and low-level software languages like C and OpenCL coupled with high-level synthesis (HLS) tools that typically produce designs that are far less efficient. Functional languages with parallel patterns are a better fit for hardware generation because they provide high-level abstractions to programmers with little experience in hardware design and avoid many of the problems faced when generating hardware from imperative languages. In this paper, we identify two important optimizations for using parallel patterns to generate efficient hardware: tiling and metapipelining. We present a general representation of tiled parallel patterns, and provide rules for automatically tiling patterns and generating metapipelines. We demonstrate experimentally that these optimizations result in speedups up to 39.4× on a set of benchmarks from the data analytics domain.

show abstract