Fine-Grain Checkpointing with In-Cache-Line Logging

Cohen, Nachshon; Aksun, David T.; Avni, Hillel; Larus, James R.

doi:10.1145/3297858.3304046

Cited by 27 publications

(11 citation statements)

References 26 publications

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“…Persistent buffering reduces the excessive flush and fence overhead by allowing flushes between independent cache lines to be reordered. Persistent coalescing facilitates batching multiple cache line flushes to the same cache line [12,13]. Recipe-based conversion inserts a flush and fence operation after each store.…”

Section: Discussionmentioning

confidence: 99%

Recipe

Lee

Mohan

Kashyap

et al. 2019

Proceedings of the 27th ACM Symposium on Operating Systems Principles

120

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We present Recipe, a principled approach for converting concurrent DRAM indexes into crash-consistent indexes for persistent memory (PM). The main insight behind Recipe is that isolation provided by a certain class of concurrent in-memory indexes can be translated with small changes to crash-consistency when the same index is used in PM. We present a set of conditions that enable the identification of this class of DRAM indexes, and the actions to be taken to convert each index to be persistent. Based on these conditions and conversion actions, we modify five different DRAM indexes based on B+ trees, tries, radix trees, and hash tables to their crash-consistent PM counterparts. The effort involved in this conversion is minimal, requiring 30-200 lines of code. We evaluated the converted PM indexes on Intel DC Persistent Memory, and found that they outperform state-of-the-art, hand-crafted PM indexes in multi-threaded workloads by up-to 5.2×. For example, we built P-CLHT, our PM implementation of the CLHT hash table by modifying only 30 LOC. When running YCSB workloads, P-CLHT performs up to 2.4× better than Cacheline-Conscious Extendible Hashing (CCEH), the state-of-the-art PM hash table.

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Section: Discussionmentioning

confidence: 99%

Recipe

Lee

Mohan

Kashyap

et al. 2019

Proceedings of the 27th ACM Symposium on Operating Systems Principles

120

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“…In future work, we try to integrate other state of the art concurrency control protocols with modern recovery protocols including some write ahead logging techniques [17,22], write behind logging [1], and checkpointing [3]. We also try to use novel NVRAM emulators to improve the quality of the emulation of NVRAM accesses.…”

Section: Discussionmentioning

confidence: 99%

Integration of TicToc Concurrency Control Protocol with Parallel Write Ahead Logging Protocol

Nakamura

Kawashima

Tatebe

2019

IJNC

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A transactional system consists of a concurrency control system and a recovery system. TicToc is one of the state of the art concurrency control protocols today, but it lacks recovery system. We studied the ways to integrate TicToc and recovery system. For efficiency, we adopted a parallel write ahead logging scheme for the recovery system. There are two methods to optimize the logging. First method is early lock release which executes lock release early on data objects. Second method is group commit which executes batched logs transfer to storage from memory. We integrated a transactional system consisted by TicToc and P-WAL logging system assuming non-volatile memory. We found that the two optimization methods incur performance degradation when storage access latency is equivalent to that of NVRAM.

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“…Once the system crashes, all or none of the data modifications in the interval become visible. The existing studies determine the interval length based on either a user-defined value [10,40] or application semantics [7]. 1 We distinguish cache line and cache block in the paper.…”

Section: Optimization Of Cache Line Flushingmentioning

confidence: 99%

“…They propose to decouple tree leaves from internal nodes and only maintain the persistency of leaf nodes. In-cacheline log [10] supports finegrained checkpointing that writes the cache hierarchy to PM at the beginning of each epoch. They place undo log and its logged data structure in the same cache line to reduce CLF.…”

Section: Related Workmentioning

confidence: 99%

Ribbon

Ren

Liu

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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Cache line flushing (CLF) is a fundamental building block for programming persistent memory (PM). CLF is prevalent in PM-aware workloads to ensure crash consistency. It also imposes high overhead. Extensive works have explored persistency semantics and CLF policies, but few have looked into the CLF mechanism. This work aims to improve the performance of CLF mechanism based on the performance characterization of well-established workloads on real PM hardware. We reveal that the performance of CLF is highly sensitive to the concurrency of CLF and cache line status. We introduce Ribbon, a runtime system that improves the performance of CLF mechanism through concurrency control and proactive CLF. Ribbon detects CLF bottleneck in oversupplied and insufficient concurrency, and adapts accordingly. Ribbon also proactively transforms dirty or non-resident cache lines into clean resident status to reduce the latency of CLF. Furthermore, we investigate the cause for low dirtiness in flushed cache lines in in-memory database workloads. We provide cache line coalescing as an applicationspecific solution that achieves up to 33.3% (13.8% on average) improvement. Our evaluation of a variety of workloads in four configurations on PM shows that Ribbon achieves up to 49.8% improvement (14.8% on average) of the overall application performance. CCS CONCEPTS • Hardware → Emerging technologies; • Computer systems organization → Multicore architectures; • Software and its engineering → Concurrency control.

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Fine-Grain Checkpointing with In-Cache-Line Logging

Cited by 27 publications

References 26 publications

Recipe

Recipe

Integration of TicToc Concurrency Control Protocol with Parallel Write Ahead Logging Protocol

Ribbon

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