Fine-grained characterization of process variation in FPGAs

Abstract

Abstract-As semiconductor manufacturing continues towards reduced feature sizes, yield loss due to process variation becomes increasingly important. To address this issue on FPGA platforms, several variation aware design (VAD) methodologies have been proposed. In this work we present a practical method of process variation characterization (PVC) to facilitate VAD using only intrinsic FPGA resources. The scheme is based on measuring the difference between ring oscillator (RO) delay at different locations within a die, and can be used to perform process variation characterization for LE delays and interconnect delays including direct connection, double wire and hex wires. The difference in loop delays can also be estimated from equations using parameters extracted from primitives and compared with direct measurements. On a Xilinx Spartan-3e device, it was found that the error between the estimated and measured values was on average less than 10%.

Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework

“…For this purpose, we incorporate the VP technique into the recycled FPGA detection flow. As the performances of neighboring CLBs in FPGA are very similar [14], [15], the sparse assumption is strongly supported, and our expectations are high that the VP technique will work very well in our recycled FPGA detection process. With this method, the fingerprinting measurement is assumed as with [4] to represent g(x, y) using the grid information in the FPGA die, where the target performance g is the RO frequency.…”

“…The VP technique utilizes the sparsity of frequency-domain components on the spatial process variation for the prediction. As the process variation on an FPGA gradually changes [14], [15], its high-frequency components are almost zero. Hence, the VP technique can be incorporated into the fingerprinting technique with remarkable affinity.…”

Grok-Lab

“…[18] and [17] take only a single measure within each LAB or CLB and make no attempt to characterize within-LAB variation. The most closely related technique used in [3] and [20] takes the difference between two ring oscillators to extract subcluster delays. However, this approach fails to account for the unique interconnect delay between pairs of LUTs, nor is it able to account for register delays.…”

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices

“…Nevertheless, in the field of reconfigurable devices such as Field Programmable Gate Arrays (FPGAs), sub-optimal approaches such as imposing guard-bands are still utilized to accommodate the Process, power supply Voltage, and Temperature (PVT) variations, and the maximum allowable clock frequencies reported by vendor synthesis, placement and routing tools are significantly lower than the ones that the device can really deliver [9]. Although there is ongoing research on the performance reliability and improvement of reconfigurable devices [10], [11], none demonstrate the value and effectiveness of replica circuit for PVT. This is the first work that introduces replica circuits in reconfigurable devices addressing PVT variations as far as the authors have investigated.…”