FinFET-a quasi-planar double-gate MOSFET

Tang, Shumin; Chang, Leland; Lindert, N.; Choi, Yang‐Kyu; Lee, Wen‐Chin; Huang, Xuejue; Subramanian, Vivek; Bokor, Jeffrey; King, Tsu‐Jae; Hu, Chenming

doi:10.1109/isscc.2001.912568

Cited by 62 publications

(47 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2, improvements in fanout of four (FO4) inverter delay over bulk devices are in the 30%-40% range. The amount of improvement shown here is smaller than that reported in [7] due primarily to the realistic doping profiles used. Series resistance is, thus, considered in this work, which lessens the improvements associated with the intrinsic device structure.…”

Section: Circuit Performance Enhancement Of Thin-body Mosfetscontrasting

confidence: 63%

“…However, even if this is achievable, it will likely result in the degradation of device performance. Because thin-body devices can control short-channel effects with only intrinsic doping in the channel, significant performance enhancements can be expected [7].…”

Section: Circuit Performance Enhancement Of Thin-body Mosfetsmentioning

confidence: 99%

“…Another feature of spacer lithography is that it can double the pattern density achievable by lithography. This is important in the FinFET structure because in order to obtain higher drive current multiple fins must be placed parallel-all straddled by a single-gate line [7]. The achievable fin pitch, thus, determines the amount of layout area required for a device.…”

Section: Double-gate Finfetmentioning

confidence: 99%

See 2 more Smart Citations

Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

Self Cite

219

View full text Add to dashboard Cite

show abstract

Section: Circuit Performance Enhancement Of Thin-body Mosfetscontrasting

confidence: 63%

Section: Circuit Performance Enhancement Of Thin-body Mosfetsmentioning

confidence: 99%

Section: Double-gate Finfetmentioning

confidence: 99%

See 1 more Smart Citation

Extremely scaled silicon nano-CMOS devices

Chang¹,

Choi

Ha³

et al. 2003

Proc. IEEE

Self Cite

219

View full text Add to dashboard Cite

show abstract

“…In order to overcome these problems, new technologies are adopted like FinFET. The FinFET have multi-gate structure which improves mobility, negligible short channel effects, minimum random dopant fluctuations, reduced parasitic junction capacitance and hence improved area efficiency [1][2][3][4][5][6][7]. Double Gate FinFET has two gates, one is front gate and other is back gate, it provides flexibility in design with low power and delay.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of FinFET based Carry save Adder Cell with Predictive Technology Models

Baghel¹,

Kaur²,

Singh³

2015

IJCA

View full text Add to dashboard Cite

As scaling of conventional metal-oxide-semiconductor field effect transistor is approaching its fundamental and technological limits, alternate device solutions are being developed. FinFET is rapidly replacing conventional CMOS transistors as it offer lot of improvements in power consumption, propagation delay and propagation delay product (PDP). This paper presents design & simulation of a double gate FinFET based ultra low power 2-bit Carry Save Adder (CSA) cell. A comprehensive comparison of FinFET and CMOS based 2-bit carry save adder has been performed. The CMOS & FinFET based 2-bit carry save adder circuits are evaluated at 32nm & 45nm nanoscale technology nodes using Predictive Technology Models (PTM). At 45nm technology node, the FinFET based carry save adder results shows average power consumption reduction of 39.75%; propagation delay reduction of 92.50% and a propagation delay product (PDP) improvement of 94.42% as compared to CMOS counterparts. The FinFET based carry save adder results shows average power consumption reduction of 42.19%; propagation delay reduction of 86.86% and a propagation delay product (PDP) improvement of 92.22% as compared to CMOS based carry save adder at 32nm technology node.

show abstract

“…One of the promising structures is FinFET ( Fig. 1(d)) [8]. Double gate devices with isolated gates (independent gates) are also being developed [9][10].…”

mentioning

confidence: 99%

Double-gate SOI devices for low-power and high-performance applications

Roy

Mahmoodi

Mukhopadhyay

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

View full text Add to dashboard Cite

Abstract:Double-Gate (DG) IntroductionThe scaling of conventional bulk CMOS technology is facing great challenges due to increased leakage and process variations with scaling down of device dimensions. Channel engineering techniques such as retrograde well and halo implantation are introduced to improve scalability and performance of such devices ( Fig. 1(a)) [1,2]. However, the scalability of such a device structure is limited due to increased short channel effects [3]. This has motivated the need for nonclassical silicon devices to extend CMOS scaling beyond 45nm node ( Fig. 1(b-d)). Ultra thin body SOI FETs employ very thin silicon body to achieve better control of the channel by the gate, and hence, reduced leakage and short channel effects. Use of intrinsic or lightly doped body reduces threshold voltage (Vt) variations due to random dopant fluctuations [4] and enhances the mobility of careers in the channel region and therefore ON current. In these devices, there can be a weak common back gate that is shared as a common substrate among all the transistors. Such a process is referred to as Ground Plane SOI (GP-SOI) [31]. Better scalability can be achieved by introduction of a second gate at the other side of the body of each transistor resulting in a Double Gate (DG) SOI structure ( Fig. 1(c)). Due to excellent control of short channel effects, double-gate SOI devices have emerged as the device of choice for circuit design in sub-50nm regime [5]. Low subthreshold leakage and higher ON current in DG devices make them suitable for circuit design in sub-50nm regime [6][7]. There are a variety of device structures suitable for double gate technologies. One of the promising structures is FinFET ( Fig. 1(d)) [8]. Double gate devices with isolated gates (independent gates) are also being developed [9][10]. Independent gate option can be useful for low power and mixed signal applications [10][11][12][13][14]. Such developments at the device level provide opportunities for new ways of circuit design for low power and high performance. In this paper, we first review the device design options for the double gate device structures (Section 2). Then, we discuss the circuit design options using such devices for logic and memory applications (Section 3 and 4). Double Gate SOI DevicesA classification of DG devices and their implications on circuit design is illustrated in Fig. 2. There are two main device processes possible for DG devices ( Fig. 2 and 3), namely (a) symmetric device with same gate material (e.g. near-midgap metals) and oxide thickness for the front and the back gate [15][16] and (b) asymmetric device with different strengths for front and back gates. Different strengths can be obtained by using either different oxide thickness (asymmetric oxide) [17] or materials of different work-function (e.g. n+ poly and p+ poly) for the front and the back gate (asymmetric work-function) [15].Regardless of the underlying device process, DG devices can also be classified in terms of their structure (Fig. 2). Typicall...

show abstract

FinFET-a quasi-planar double-gate MOSFET

Cited by 62 publications

References 5 publications

Extremely scaled silicon nano-CMOS devices

Extremely scaled silicon nano-CMOS devices

Performance Analysis of FinFET based Carry save Adder Cell with Predictive Technology Models

Double-gate SOI devices for low-power and high-performance applications

Contact Info

Product

Resources

About