Spectroscopic ellipsometry was used to investigate the oxidation of pure Hf films on silicon for the formation of HfO2 (hafnium oxide) gate-dielectric films in advanced complementary metal-oxide-semiconductor field-effect transistors. Absorption coefficients near the absorption edge were extracted using the data inversion method, in which the optical constants for short wavelengths were calculated using the film thickness determined from long-wavelength data. The extracted optical band gap of 5.7 eV matches well with published data, and a curve shift due to crystallization was detected. In addition, an extra absorption peak corresponding to electron transition from the valence band to a defect energy level was observed in the range 4.5–5.0 eV above the valence-band edge. The 1.2 eV energy difference between the conduction-band edge and the edge of this extra peak is close to the electron trap energy level reported elsewhere. The intensity of the detected peak was clearly correlated with leakage current and near-interface trap densities. Based on the annealing condition dependence of the extra absorption peak, the defects are likely oxygen vacancies within the HfO2 film.

Gate-induced drain leakage (GIDL) current is investigated in single-gate (SG) ultra-thin body field effect transistor (FET), symmetrical double-gate (DG) FinFET, and asymmetrical DG metal oxide semiconductor field effect transistor (MOSFET) devices. Measured reductions in GIDL current for SG and DG thin-body devices are reported for the first time. The thin-body devices exhibit much lower GIDL current than bulk-Si MOSFETs, and the GIDL is found to decrease with decreasing body thickness. These results can be explained by the reduction in transverse electric field at the surface of the drain and the increase in transverse effective mass with decreasing body thickness.

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are 1) the writeand-verify (WAV) writing of four-level resistance states and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diodeswitch phase change memory cells with 90nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 10 8 cycles, respectively. In addition, they are nondestructively readable above 10 7 read pulses at 100ns and 1uA. IntroductionPhase-change random access memory (PRAM) is most promising to realize a multi-level cell (MLC) operation because it has very wide range of resistance across two orders of magnitude or the higher, with respect to writing current. According to the PRAM road map [1], it is expected that highest memory densities of PRAM become comparable to conventional memories such as NOR Flash and DRAM in coming years when MLC operation is fully accomplished. In this paper, we systematically investigated a four-level (two-bit) cell operation in diode-switch phase change memory cells with 90nm technology and discussed its possibilities and issues as well.

As Si has faced physical limits on further scaling down, novel semiconducting materials such as 2D transition metal dichalcogenides and oxide semiconductors (OSs) have gained tremendous attention to continue the ever‐demanding downscaling represented by Moore's law. Among them, OS is considered to be the most promising alternative material because it has intriguing features such as modest mobility, extremely low off‐current, great uniformity, and low‐temperature processibility with conventional complementary‐metal–oxide–semiconductor‐compatible methods. In practice, OS has successfully replaced hydrogenated amorphous Si in high‐end liquid crystal display devices and has now become a standard backplane electronic for organic light‐emitting diode displays despite the short time since their invention in 2004. For OS to be implemented in next‐generation electronics such as back‐end‐of‐line transistor applications in monolithic 3D integration beyond the display applications, however, there is still much room for further study, such as high mobility, immune short‐channel effects, low electrical contact properties, etc. This study reviews the brief history of OS and recent progress in device applications from a material science and device physics point of view. Simultaneously, remaining challenges and opportunities in OS for use in next‐generation electronics are discussed.

Over the last few decades, the research on ferroelectric memories has been limited due to their dimensional scalability and incompatibility with complementary metal‐oxide‐semiconductor (CMOS) technology. The discovery of ferroelectricity in fluorite‐structured oxides revived interest in the research on ferroelectric memories, by inducing nanoscale nonvolatility in state‐of‐the‐art gate insulators by minute doping and thermal treatment. The potential of this approach has been demonstrated by the fabrication of sub‐30 nm electronic devices. Nonetheless, to realize practical applications, various technical limitations, such as insufficient reliability including endurance, retention, and imprint, as well as large device‐to‐device‐variation, require urgent solutions. Furthermore, such limitations should be considered based on targeting devices as well as applications. Various types of ferroelectric memories including ferroelectric random‐access‐memory, ferroelectric field‐effect‐transistor, and ferroelectric tunnel junction should be considered for classical nonvolatile memories as well as emerging neuromorphic computing and processing‐in‐memory. Therefore, from the viewpoint of materials science, this review covers the recent research focusing on ferroelectric memories from the history of conventional approaches to future prospects.