FinFET-based 11T sub-threshold SRAM with improved stability and power

Abbasian, Erfan; Birla, Shilpi; Asadi, Abbas; Sofimowloodi, Sobhan

doi:10.1080/00207217.2022.2121987

International Journal of Electronics

2022

DOI: 10.1080/00207217.2022.2121987

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FinFET-based 11T sub-threshold SRAM with improved stability and power

Erfan Abbasian

Shilpi Birla

Abbas Asadi

et al.

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Cited by 4 publications

References 32 publications

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Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Praveen,

Singh

2024

Circuit Theory & Apps

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The excessive power usage in modern digital equipment is triggered by memory arrays, mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working to create an SRAM cell that is fast, highly stable, and uses little power. However, the traditional SRAM cells have instability and read/write failure at scaled technology nodes. This study proposes a Differential Power Schmitt‐Trigger Logic 9 Tcompute SRAM (DPSTL‐9 TCSRAM) cell design with high read‐and‐write stability and low energy consumption. In SRAM cells, the sensing amplifier (SA), pre‐charge circuit, row decoder, and column decoder are the primary operational elements. Through the use of a single‐bitline (SBL) configuration and a one‐sided Schmitt‐trigger (ST) inverter (STI), the proposed deisgn cell achieves an outstanding read stability performance. In this work, the differential Power Generation (DPG) technique is employed to improve the architecture's writing capacity. The standard AND gates are combined with Schmitt‐trigger logic AND gates to improve noise tolerance while consuming less power and taking up less space. Instead of using a power‐gating mechanism, this research focuses on modifying a power delay product (PDP) circuit to increase the cell's read‐and‐write operation efficiency. The modified decoupled SA plays a major role in the access time and provides significant benefits in terms of read latency. Tanner EDA Tool platform version 16.0 can be used to execute the specified design. The performance metrics of stability, area, latency, and power analysis are examined, and also, the Monte Carlo simulation and reliability simulation are conducetd to show the efficacy of the proposed design.

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Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Praveen,

Singh

2024

Circuit Theory & Apps

View full text Add to dashboard Cite

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Single Ended Read Decoupled High Stable 9T CNTFET SRAM for Low Power Applications

Elangovan,

Akash,

El‐Meligy

et al. 2024

Int J Numerical Modelling

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In wireless sensor networks, conserving power is vital for prolonging battery life. This research introduces a groundbreaking solution: a 9T carbon nanotube‐field effect transistor (CNTFET) based SRAM cell (9T SRAM) designed to optimize power consumption and stability. Through meticulous analysis, the performance of this 9T SRAM cell is quantified. Power consumption metrics reveal impressive figures: the write, hold, read, and dynamic power are measured at 0.21 nW, 0.32 nW, 15.28 μW, and 8.09 μW, respectively. Furthermore, the Write SNM (WSNM), Hold SNM (HSNM), and Read SNM (RSNM) are found to be 380.11, 390.22, and 390.31 mV, respectively, indicating robust stability. The proposed bit cell has a write and read delay of 95.1 and 39.6 pS, respectively. Incorporating stacked transistors diminishes power consumption, while the decoupled read technique boosts the stability of the proposed bit cell. By comparing these results with existing SRAM cells, the superiority of the proposed 9T SRAM cell in terms of power efficiency becomes evident. Notably, it outperforms earlier models, making it an ideal candidate for integration into wireless sensor networks. These findings are supported by simulations conducted using HSPICE, alongside a 32 nm CNTFET model sourced from Stanford University.

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Single-sided gate-wrap-around CNTFET SRAM cell for utilization in reliable IoT-based platforms

Darabi

Salehi

Abiri

2023

AEU - International Journal of Electronics and Communications

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FinFET-based 11T sub-threshold SRAM with improved stability and power

Cited by 4 publications

References 32 publications

Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Single Ended Read Decoupled High Stable 9T CNTFET SRAM for Low Power Applications

Single-sided gate-wrap-around CNTFET SRAM cell for utilization in reliable IoT-based platforms

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