2016 IEEE International Reliability Physics Symposium (IRPS) 2016
DOI: 10.1109/irps.2016.7574555
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FinFET SCR structure optimization for high-speed serial links ESD protection

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Cited by 11 publications
(2 citation statements)
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“…In order to achieve efficient ESD protection for Fin-FET chips, the diode-triggered Fin-silicon-controlled rectifiers (DTFSCR), with high current conduction efficiency and controllable trigger voltage, have been explored lately [2][3][4].…”
Section: Introductionmentioning
confidence: 99%
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“…In order to achieve efficient ESD protection for Fin-FET chips, the diode-triggered Fin-silicon-controlled rectifiers (DTFSCR), with high current conduction efficiency and controllable trigger voltage, have been explored lately [2][3][4].…”
Section: Introductionmentioning
confidence: 99%
“…A checkerboard SCR has been proposed to improve the leakage current and parasitic capacitance characteristics. However, due to the large space from anode to cathode (SAC) derived from stacking topology, the on-resistance and clamping voltage of this structure will deteriorate inevitably [2]. Besides, a rotated DTFSCR has been implemented to reduce the on-resistance by minimizing the SAC, but the triggering diode inside such a device will consume a considerable part of the layout area, resulting in a decrease in area efficiency [3].…”
Section: Introductionmentioning
confidence: 99%