FinFET SRAM cell with improved stability and power for low power applications.

Birla, Shilpi

doi:10.29292/jics.v14i2.57

Cited by 8 publications

(6 citation statements)

References 24 publications

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“…On the other hand, the static power dissipation occurs due to various leakage phenomena and resulting current, which flows through various terminals of the device. The three dominant components in nano-scaled CMOS devices are subthreshold leakage, oxide tunneling current and reverse-biased junction current [25]. Though the leakage phenomenon mentioned above refers to FinFET also but, FinFET devices have improved gate control to suppress these currents due to its multi-gate structure.…”

Section: B Power Dissipationmentioning

confidence: 99%

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Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

Duari

Birla

Singh³

2020

JICS

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Static Random-Access Memory cells with ultralow leakage and superior stability are the primary choice of embedded memories in contemporary smart devices. This paper presents a novel 8T SRAM cell with reduced leakage and improved stability. The proposed SRAM cell uses a stacking effect to reduce leakage and transmission gate as an access transistor to enhance stability. The performance of the proposed 8T SRAM cell with a stacked transistor has been analyzed based on the power consumption and static noise margin (RSNM, HSNM, and WSNM). The power consumption in the case of FinFET based 8T cell is found to be 572 pW at 22 nm technology node, which is reduced by a factor nearly as compared to that of CMOS based 8T cell. Further, in the case of FinFET based novel 8T SRAM cell at 22 nm technology node, the power consumption is found to be reduced by a factor of as compared to that of FinFET based conventional 6T SRAM cell. WSNM, HSNM, and RSNM of the 8T SRAM cell designed with FinFET logic are observed as 240 mV, 370 mV, and 120 mV respectively at 0.9 V supply voltage. When comparing with conventional 6T FinFET Cell, the proposed Cell shows 20%, 5.11%, and 7% improvement in WSNM, HSNM, and RSNM, respectively. The sensitivity of SNM with temperature variation is also analyzed and reported. Further, the results obtained confirm the robustness of the proposed SRAM cells as compared to several recent works.

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Section: B Power Dissipationmentioning

confidence: 99%

“…These cells are designed to operate in the subthreshold region with a supply voltage of less than 4V. 11T FinFET cell with a header transistor scheme with improved stability and low power has been reported [25].…”

Section: Introductionmentioning

confidence: 99%

Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

Duari

Birla

Singh³

2020

JICS

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“…Thus, technologies like CNTs (Carbon Nano Tubes), TFETs (Tunnel FETs) [10], and FinFETs [8,9]. [11,12] have emerged as viable alternatives to CMOS. Of these options, FinFET technology [11][12] is selected as the most promising successor to CMOS.…”

Section: Introductionmentioning

confidence: 99%

“…[11,12] have emerged as viable alternatives to CMOS. Of these options, FinFET technology [11][12] is selected as the most promising successor to CMOS. Increased speed, greater drive current for a given transistor footprint, decreased leakage, elimination of random dopant fluctuation, decreased power consumption, enhanced mobility, and improved transistor scaling are just a few of the advantages of FinFET over bulk CMOS.…”

Section: Introductionmentioning

confidence: 99%

Design of SRAM Cell using Modified Lector and Dual Threshold Method Based on FINFET

Ramesh Gullapally

2023

IJRITCC

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FinFET (Fin Field Effect Transistor) is a new technology that satisfies the demand for a superior storage system by improving transistor circuit design (SS). CMOS devices experience a wide range of issues due to the gate's diminishing ability to control the channel. Increased total production costs are a few of these disadvantages. But this store needs to dissipate less power, have a quick access time, and a low leakage current. The increased power dissipation and leakage current of traditional CMOS-based SRAM (Static RAM) architectures cause a sharp decline in performance. The nanoscale gadget called FinFET is being introduced for use in SRAM fabrication due to its 3D gate architecture. The adoption of FinFET has helped boost overall performance in terms of efficiency, power, and footprint. And because it is immune to SCEs, FinFET has become the transistor of choice. In this study, we have examined a number of FinFET-based SRAM cells and compared them with CMOS technology. We have also suggested a novel 14T SRAM design that uses the Dual Threshold Method and Modified Lector Approach with FinFET, and it is implemented for the 1bit, 4bit, and 8bit.

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“…Therefore, CMOS scaling has now come to a limit with the following possible alternatives such as FinFETs [8], TFET (Tunnel FET) [9], and CNTs (Carbon Nano Tubes) [10]. Among these alternatives, FinFET technology [11][12] is chosen as the best option for replacing CMOS. FinFET provides several advantages over bulk CMOS, for instance, higher speed, higher drive current for a given transistor footprint, lower leakage, no random dopant uctuation, lower power consumption, better mobility and transistor scaling.…”

Section: Introductionmentioning

confidence: 99%

A Review On Sram Memory Design Using Finfet Technology

Lakshmi¹,

Kamaraju²

2022

Preprint

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An innovative technology named FinFET (Fin Field Effect Transistor) has been developed to offer better transistor circuit design and to balance the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices face some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents etc. However, the memory must have less power dissipation, short access time and low leakage current. The traditional design of SRAM (Static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a Nano-scaled device named FinFET is introduced for designing SRAM since it has three dimensional (3D) design of the gate. FinFET has been used to improve the overall performance, which includes efficiency, power, and area. Moreover, FinFET has been chosen as a transistor of choice because it is not affected by SCEs. In this work, we have reviewed various FinFET based SRAM cells, performance metrics and the comparison over different technologies.

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FinFET SRAM cell with improved stability and power for low power applications.

Cited by 8 publications

References 24 publications

Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

Dual Port 8T SRAM Cell Using FinFET & CMOS Logic for Leakage Reduction and Enhanced Read & Write Stability

Design of SRAM Cell using Modified Lector and Dual Threshold Method Based on FINFET

A Review On Sram Memory Design Using Finfet Technology

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