FinFlash with buried storage ONO layer for flash memory application

Chang, Sung‐Jae; Bawedin, M.; Xiong, Wade; Lee, Jong‐Hyun; Lee, Jung‐Hee; Cristoloveanu, S.

doi:10.1016/j.sse.2011.11.008

Cited by 7 publications

(6 citation statements)

References 4 publications

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“…1b) and to show multi-bit capability (29). Figure 5 shows the URAM implementation within a FinFET (28). The NVM charge is detected, via coupling effect, by the current flowing at the front-gate.…”

Section: Unified Memorymentioning

confidence: 99%

“…The URAM concept has been demonstrated by adding a NVM charge trapping layer (for example, oxide/nitride/oxide (ONO) stack) to the 1T-DRAM (Fig. 5a) (25)(26)(27)(28)(29)(30). Electrons or holes are injected (by Fowler-Nordheim or hot carrier mechanisms) and trapped into the silicon nitride In the meantime, the floating body is used as a storage volume for the 1T-DRAM function.…”

Section: Unified Memorymentioning

confidence: 99%

“…5a, the back-gate bias was used to store electrons (V GB > 0) or holes (V GB < 0) in the nitride. Due to 3D coupling effects, the NVM is more efficient in short and not too narrow FinFETs (28).…”

Section: Unified Memorymentioning

confidence: 99%

“…Even more ambitious is the 'unified' memory (25)(26)(27)(28)(29)(30)(31) which combines, within a single SOI transistor, volatile and nonvolatile memory functionalities as well as multiple memory states.…”

Section: Introductionmentioning

confidence: 99%

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(Invited) Special Memory Mechanisms in SOI Devices

Cristoloveanu¹,

Bawedin²,

Navarro³

et al. 2015

ECS Trans.

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Several types of floating-body capacitorless 1T-DRAM memory cells with planar SOI or multi-gate configuration are reviewed and compared. We show that 1T-DRAMs are also compatible with the 'unified memory' paradigm which aims at combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We focus on our recently proposed concepts (MSDRAM, A2RAM and Z 2 -FET), by addressing the device architecture and fabrication, operating mechanisms, and scaling issues. Experimental results together with numerical simulations indicate the directions for performance optimization.

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Section: Unified Memorymentioning

confidence: 99%

Section: Unified Memorymentioning

confidence: 99%

Section: Unified Memorymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

(Invited) Special Memory Mechanisms in SOI Devices

Cristoloveanu¹,

Bawedin²,

Navarro³

et al. 2015

ECS Trans.

Self Cite

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show abstract

“…In our SOI FinFETs fabricated on buried SiO 2 -Si 3 N 4 -SiO 2 (ONO) layers, the nitride can efficiently trap/detrap nonvolatile charges by back-gate or drain biasing. The charges stored in the nitride are sensed at the front-channel of the transistor by 'remote' gate coupling (4). The advantage of this approach comes from the separation of the storage medium and reading interface.…”

Section: Introductionmentioning

confidence: 99%

Multi-Bit Unified Memory Concept in FinFETs with ONO Buried Insulator

Chang

Bawedin

Xiong³

et al. 2013

ECS Trans.

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Transient mechanisms in SOI FinFETs fabricated on ONO buried insulator were investigated for multi-bit unified memory operation. In nonvolatile memory applications, charges are trapped/detrapped in the nitride buried layer by back-gate or drain bias and are sensed at the front-channel. Volatile charges are generated by impact ionization and stored in the silicon body of the transistor. The volatile charges are sensed at the back-channel. Our experimental results demonstrate multi-bit unified memory by advantageously combining the two memory modes. Systematic measurements reveal that the impact of the nonvolatile charges located near the drain side on the volatile sensing margin is larger than the charges located at the opposite side.

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NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

Bohara

Vishvakarma

2019

J Comput Electron

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FinFlash with buried storage ONO layer for flash memory application

Cited by 7 publications

References 4 publications

(Invited) Special Memory Mechanisms in SOI Devices

(Invited) Special Memory Mechanisms in SOI Devices

Multi-Bit Unified Memory Concept in FinFETs with ONO Buried Insulator

NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

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