Finite State Machine Implementation in FPGAs

Kubátová, Hana

doi:10.1007/0-387-28327-7_15

Cited by 7 publications

(3 citation statements)

References 4 publications

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“…2. Example of headers KISS2 [4] Due to application of TimeQuest Timing Analyzer from Tools Menu Quartus Altera [7] there was estimated time of performance for hybrid of finite state machine from [1] and [5,6]. The results from Report Fmax Summary are for Auto and One-Hot Encoding -854.7MHz, for Sequential and Minimal Bits 1000 MHz, .Johnson and Gray encoding 1001 MHz, which partially coincide with results from [2].…”

Section: Using Benchmark Tests For Compare Speed Of Performance For Different State Memory Encodingsupporting

confidence: 60%

Using Benchmark Tests for Research State Memory Encoding in Finite State Machine

Zaichenko¹,

Zaichenko²,

Galkin³

et al. 2021

2021 III International Scientific and Practical Conference Theoretical and Applied Aspects of Device Development on Microcontro

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Abstract?The synthesizer will automatically assign the state memory codes based on the most effective use of the target technology (e.g., binary, gray code, one-hot) in FPGA. But exists alternative, when user by himself choose type of memory encoding. There was considered user defined state coding method for Quartus Altera. Keywords?FPGA, finite state machine, state memory, memory coding, synthesizer, one-hot, sequential, johnson, optimization, speed of performance

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Section: Using Benchmark Tests For Compare Speed Of Performance For Different State Memory Encodingsupporting

confidence: 60%

Using Benchmark Tests for Research State Memory Encoding in Finite State Machine

Zaichenko¹,

Zaichenko²,

Galkin³

et al. 2021

2021 III International Scientific and Practical Conference Theoretical and Applied Aspects of Device Development on Microcontro

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“…To ensure that two different synthesis methods are used: modular synthesis and architectural synthesis but other known can also considered [9], [24], [25]. In addition, different description styles are applied: assertion based [21], [26], [18] and structural RTL description [27], [28].…”

Section: Synthesis and Implementationmentioning

confidence: 99%

Dual synthesis of Petri net based dependable logic controllers for safety critical systems

Bukowiec

Tkacz

Adamski

et al. 2014

2014 7th International Conference on Human System Interactions (HSI)

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In the paper, implementation of application specific logic controller for safety critical systems by means of Petri nets is described. The solution is based on duplicated main control unit and results comparison from both units. The design process of algorithm with use of Petri net is common for both unit. The hardware duplication is obtained during dual synthesis process. This process uses two different logic synthesis methods to obtain two different architectures for both control units. Such design flow simplify the process of realization of safety critical logic controllers.

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“…their description and verification, and their implementation. Several approaches based on formal models have been proposed, for example the B-method [1] and more "usual" discrete event system (DES) modeling techniques such as finite state machines (FSM) [3], StateCharts [23] and Petri nets (PN) [25]. PN have been widely used for the study of complex systems [4] [5] because of their easily understood graphic representation -which allows parallelism, choice, synchronization, resource sharing, etc.…”

Section: Introductionmentioning

confidence: 99%

Petri Net Based Rapid Prototyping of Digital Complex System

Andreu

Souquet²,

Gil³

2008

2008 IEEE Computer Society Annual Symposium on VLSI

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This paper deals with the automatic translation of interpreted generalized Petri Nets with time into VHDL, for rapid prototyping on programmable logic device purposes. This approach is based on the component orientation of the VHDL language, and defines two elementary VHDL components: the place and the transition. This transition component is a "pivot" element of the approach, since it supports all the interconnections between places and transitions (i.e. it allows the structure of the PN to be built). Moreover, with the aim to reduce power consumption, we proposed to control the VHDL component's activity according to an approach based on the "activity propagation" principle since PNs are oriented graphs.

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Finite State Machine Implementation in FPGAs

Cited by 7 publications

References 4 publications

Using Benchmark Tests for Research State Memory Encoding in Finite State Machine

Using Benchmark Tests for Research State Memory Encoding in Finite State Machine

Dual synthesis of Petri net based dependable logic controllers for safety critical systems

Petri Net Based Rapid Prototyping of Digital Complex System

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