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The paper presents an application of UML technology in a discrete system development process. In the process at the analysis stage UML diagrams are fundamental tool. The outcome of this stage is a basis for formal models exploited at the design stage, where the design is symbolically verified and treated as a rule-based system. Two formal models of good graphical appeal are proposed: Petri nets and state machine diagrams. Both are heavily using Boolean expressions what makes that design can easily be implemented in modern programmable structures.

The paper is concentrated on behavioral and structural specification of reconfigurable logic controllers (RLC). The initial description is given as a hierarchical modular control interpreted Petri net. On the abstract level of the logic synthesis specification is written in propositional sequent language. Rapid modeling and synthesis in FPGA can be done directly from expressions, written in the hardware description language, for example in VHDL.

Abstract. The paper describes a new method of verification of the application specific logic controllers designed with use of Petri net. The method is oriented on behavioral simulation of post synthesis models. Two different method of logic synthesis are preformed for the same control algorithm described as Petri net. Then, obtained HDL models are used for dual simulation with result comparison. It allows to detect ambiguous construct in designed control algorithm.Keywords: logic controller, Petri net, simulation. IntroductionThe paper presents a new method of dual simulation of the application specific logic controllers (ASLCs). ASLCs [1][2][3][4][5] are one of the biggest group of electronic circuits.The most classical way of designing such controllers is application of hardware description languages (HDLs) but it is annoying for designer and possibly it gives high risk of human mistake. The usage of graphical representation of control algorithm is much more conformable [6][7][8]. Now, Petri nets (PNs) [9,10] are one of the most adequate methods for formal design of such controllers [11]. It gives a simple way for representation of concurrent processes and application of interpretation gives a possibility to exchange information with environment. Additionally, there could be applied mathematical algorithms for formal analysis and verification of the designed model [12][13][14][15]. Although these algorithms are able to detect defects, like liveness or reachability, in Petri net structure but they are not able to detect nondeterministic behavior of the algorithm. Typically the nondeterministic behavior of the algorithm is caused by a human mistake and it does not affect Petri net structure. To detect such mistake there have to be performed the simulation of the control algorithm and the comparison of its results with expected ones. It is very arduous process and it does not give expected results because it is also loaded with human mistake. The solution for this problem is dual simulation [16,17] with automated results comparison. Although currently only behavioral HDL description is used for such approaches and it is oriented on increase of simulation reliability. It allows also to detect some nondeterministic behavior but while the simulation is on behavioral level not connected to a hardware realization it does not ensure that all of them will be detected and controller

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