UML Modelling in Rigorous Design Methodology for Discrete Controllers

Łabiak, Grzegorz; Adamski, Marian; Doligalski, Michał; Tkacz, Jacek; Bukowiec, Arkadiusz

doi:10.2478/v10177-012-0004-8

Cited by 12 publications

(9 citation statements)

References 7 publications

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“…The Petri net as graphical representation of algorithm [3], [29]- [31] is used as entry point to the synthesis method. The logic circuit is obtained by application of the architectural decomposition methods [18], [32].…”

Section: Discussionmentioning

confidence: 99%

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Synthesis of Macro Petri Nets into FPGA with Distributed Memories

Bukowiec¹,

Adamski²

2012

International Journal of Electronics and Telecommunications

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Abstract-In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets. Each state machine subnet is determined by one color. During the decomposition process macroplaces are expanded or replaced by doublers of macroplace. Such decomposition leads to parallel implementation of a digital system. The structured encoding of places is done by using minimal numbers of bits. Colored microoperations, which are assigned to places, are written into distributed and flexible memories. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.

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Section: Discussionmentioning

confidence: 99%

“…1a) describes control process of industrial mixer of aggregate content and water (Fig. 6) [28], [29]. Outputs of the controller are connected into valves of tanks and engine of mixer.…”

Section: Example Of Methods Applicationmentioning

confidence: 99%

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

Bukowiec¹,

Adamski²

2012

International Journal of Electronics and Telecommunications

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“…The macroplace-centered and place-centered decomposition and encoding of SM-colored Petri net is preferable from FPGA resources utilization point of view [22], [23]. Additionally it make possible flexible reusing of previously tested, encoded Petri net components.…”

Section: Simulation and Synthesismentioning

confidence: 99%

Structured Mapping of Petri Net States and Events for FPGA Implementations

Tkacz¹,

Adamski²

2013

International Journal of Electronics and Telecommunications

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Abstract-The paper presents a new method of structured encoding of global internal states and events in Reconfigurable Logic Controllers, which are directly mapped into Field Programmable Gate Arrays (FPGA). Modular, concurrently decomposed, colored state machine is chosen as a intermediate model, before the mapping of Petri net into an array structure of dedicated but very flexible and reliable digital system. The initial textual specification in formal Gentzen logic serves both as a design description for a rapid prototyping, as well as formal model, suitable for detailed computer-based reasoning about optimized and synthesized logic controller, implemented in configurable hardware. Only the selected linear subset from general, universal propositional Gentzen Logic is necessary to deduce several properties of the net, such as relations of nonconcurrency among structurally ordered macroplaces. The goal of this paper is to present the design methodology for modeling and synthesis of discrete controllers using related Petri net theory, rule-based theory (mathematical logic), and VHDL.

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“…The application of Partial Reconfiguration in the field of LCs, improve its quality not only by improving the functionality but also by reducing power consumption and minimization of the allocated resources. The application of the modern specification technics, UML language in particular [9], will simplify partial reconfiguration oriented design. Petri nets give the possibility for logic controller formal verification [10], for example by means of Gentzen reasoning techniques [11]- [13].…”

Section: Introductionmentioning

confidence: 99%

Partial Reconfiguration in the Field of Logic Controllers Design

Doligalski

Bukowiec

2013

International Journal of Electronics and Telecommunications

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Abstract-The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process.

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UML Modelling in Rigorous Design Methodology for Discrete Controllers

Cited by 12 publications

References 7 publications

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

Structured Mapping of Petri Net States and Events for FPGA Implementations

Partial Reconfiguration in the Field of Logic Controllers Design

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