Logic design of structured configurable controllers

Abstract

The paper is concentrated on behavioral and structural specification of reconfigurable logic controllers (RLC). The initial description is given as a hierarchical modular control interpreted Petri net. On the abstract level of the logic synthesis specification is written in propositional sequent language. Rapid modeling and synthesis in FPGA can be done directly from expressions, written in the hardware description language, for example in VHDL.

Dual synthesis of Petri net based dependable logic controllers for safety critical systems

“…This description is platform independent. The first one is based on rule-based specification and hierarchical encoding [2]. It is obtained as a single module.…”

“…The novel methodology of logic synthesis of concurrent digital controllers for safety critical systems is based on dual synthesis of the same Petri net model with use of differen synthesis methods. First synthesis method is based on rule-based specification and hierarchical encoding obtained from Petri net model [2]. The second one is based on architectural decomposition of logic circuit and decomposition of Petri net into state machine (SM) subnets [3], [4].…”

Structured Mapping of Petri Net States and Events for FPGA Implementations

“…Several optimization techniques could be used for getting smaller number of macrocells [1], [2], [4], [13]. One of them is decomposition of the net into coordinated state machine components, presented in this paper.In that case the number of registered cells (extended T Flip-Flops) could be reduced to nine or even more (Sections VIII, IX).…”

“…Each color recognizes one state machine module. The rules for Petri net coloring can be found in [2], [3], [5], [15].…”

“…The proposed rigorous digital design process starts from hierarchical concurrent state machine model (HCSM), which has been formally derived from modular, colored control interpreted Petri net [1], [2], [8]- [10]. The colored tokens, arcs, places and transitions separate hierarchically and concurrently related State Machine components.…”