Formal Reasoning in Logic Design of Reconfigurable Controllers

Structured Mapping of Petri Net States and Events for FPGA Implementations

“…In order to check if the Petri net is live, traps equal to siphons (deadlocks) are designed [1], [12], [15]- [17]. Sets of marked traps contained in siphons determine potential state machine subnet, present in the Petri net.…”

“…Meanwhile, loaded containers are transported (signal y 12 ) to a proper location indicated by sensor x 13 . When the ingredients are ready it is signalized by preparation of the drink is finished x 10 filling off the first tank is finished x 11 filling off the second tank is finished x 12 the carriage is in its initial location x 13 the carriage is in its target location OUTPUTS Signal Description y 1 preparation of the first ingredient y 2 preparation of the second ingredient y 3 loading containers y 4 mixing ingredients y 5 valve for emptying the first container y 6 valve for emptying the second container y 7 valve for filling the first tank y 8 valve for filling the second tank y 9 carriage movement to the initial location (right) y 10 valve for filling the first container y 11 valve for filling the second container y 12 carriage movement to the target location (left)…”

“…In order to determine the SM-subnets covering of the Petri macronet, formal reasoning using propositional Gentzen calculus was used [12], [16]- [19]. As a result of local and global state space analysis, state machine subnets are obtained.…”

Dual synthesis of Petri net based application specific logic controllers with increased safety

“…Next, places colored by the color C 2 can be encoded. Because places p 1 , p 14 , p 15 , and p 16 from the set P 2 are already encoded because they are in the set P 1 , they are removed from the set P 2 , and now P 2 = {p 3 , p 5 , p 10 , p 12 }, according to (8). Now, remaining places do not create marked cycle, so there is required to use R 2 = 3 bits, according to (6), to encode these places, and encoding starts from the code 001 (Table 1).…”

“…The first synthesis method is based on modular and symbolic encoding during the logic synthesis [15]. The second one is based on architectural decomposition of a logic circuit [16] and decomposition of Petri net into state machine subnets [16,17], in which the embedded memory blocks are utilized during synthesis process [4,8,[16][17][18].…”