Finite State Machine Logic Synthesis for Complex Programmable Logic Devices

Czerwiński, Robert; Kania, Dariusz

doi:10.1007/978-3-642-36166-1

Cited by 77 publications

(77 citation statements)

References 13 publications

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“…The resource sharing cost is calculated for each input. For reducing the address decoding costs the one hot controller is used (Kania and Czerwiński, 2013). It can be determined that multiplexing n arguments with k input LUT (look up table) with one-hot approach is given by following formula:…”

Section: Resource Sharing Mappingmentioning

confidence: 99%

On PLCs Control Program Hardware Implementation Selected Problems of Mapping and Scheduling

Milik

2015

IFAC-PapersOnLine

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The paper shows the FPGA dedicated method of mapping a PLC program written according to the IEC61131-3 standard. There is described complete synthesis process from the program description to hardware implementation through mapping and scheduling procedures. PLCs' programming languages are translated into common intermediate graph form. It enables massive parallel implementation. There is presented an originally developed graph structure with attribute edges. Finally the graph mapping methodologies are discussed. A general hardware mapping concept and algorithms for utilizing specific FPGA components are presented. An efficient mapping of the DSP48 block is shown. It attempts to utilize all features of the block in pipelined calculation model. The consideration are summarized with implementation result comparison for general hardware mapping and with use of DSP48 units.

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Section: Resource Sharing Mappingmentioning

confidence: 99%

On PLCs Control Program Hardware Implementation Selected Problems of Mapping and Scheduling

Milik

2015

IFAC-PapersOnLine

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“…It seems to us that JEDI is the best among the known state assignment algorithms (Czerwiński and Kania, 2013). It is distributed with the system SIS (Sentowich et al, 1992).…”

Section: State Of the Artmentioning

confidence: 99%

“…A lot of digital systems include control units (Baranov, 2008;Gajski et al, 2009). As follows from the works of Czerwiński and Kania (2013) or Minns and Elliot (2008), different models of finite state machines (FSMs) are used very often for representing and designing control units. In many practical cases, the model of a Mealy FSM is used for these purposes (Sklyarov et al, 2014;Micheli, 1994).…”

Section: Introductionmentioning

confidence: 99%

“…It is very important to diminish the amount of hardware consumed by an FSM logic circuit (Gajski et al, 2009;Czerwiński and Kania, 2013). Solution methods for this problem strongly depend on specific features of logic elements used for implementing the circuits (Czerwiński and Kania, 2013;Sklyarov et al, 2014). In our article, we discuss a case when field programmable gate arrays (FPGAs) are used to implement Mealy FSM logic circuits.…”

Section: Introductionmentioning

confidence: 99%

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Hardware Reduction for Lut–Based Mealy FSMs

Barkalov

Titarenko

Mielcarek

2018

International Journal of Applied Mathematics and Computer Science

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A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.

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“…3,4 As a rule, FPGA are used for implementing rather complex FSMs, 5 whereas CPLD target fast FSMs. 6,7 The majority of CPLD are based on PAL cells connected with programmable°ip-°o ps. 8,9 Each cell can be viewed as q s-input AND gates connected with an OR gate.…”

Section: Introductionmentioning

confidence: 99%

Hardware Reduction in CPLD-Based Moore FSM

Barkalov

Titarenko

Chmielewski

2014

J CIRCUIT SYST COMP

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A new two-stage method of¯nite state machines (FSMs) synthesis for PAL-based complex programmable logic devices (CPLD) is proposed. It is based on both the wide fan-in of PAL cells and existence of the classes of pseudoequivalent states of Moore FSM. The¯rst step targets decreasing for the number of PAL cells used for implementing the block of input memory functions. The second step targets decreasing for the number of PAL cells in the block of microoperations. An example of application of the proposed method is given, as well as results of experiments carried out for standard benchmarks.

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Finite State Machine Logic Synthesis for Complex Programmable Logic Devices

Cited by 77 publications

References 13 publications

On PLCs Control Program Hardware Implementation Selected Problems of Mapping and Scheduling

On PLCs Control Program Hardware Implementation Selected Problems of Mapping and Scheduling

Hardware Reduction for Lut–Based Mealy FSMs

Hardware Reduction in CPLD-Based Moore FSM

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