FIR filter implementation using bit-serial arithmetic and partial summation trees

The Mulriplier Tree FIR filter orchifecfure eliminates redundanf arithmetic elements in the consfant coejjicienr multipliers of fhe transposed form FIR filfer architecture, facilitating low hardware cosffilter implementations. This paper presents fhe Multiplier Tree FIR Filler archifecture and implemenfarion results for this architecture, A comparison of this architecture to previous FIR filter implementations i.7 presented. Remlts for 95 and 45-lap FIR filfer implementation.s show hardware cosf can he reduced significnntly with the Multiplier Tree architecture.

show abstract

The Multiplier Tree FIR filter architecture

Carreira¹,

Fox²

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

View full text Add to dashboard Cite

show abstract

The design of low-cost fixed-point FIR digital filters using an improved local search

Fox¹,

Carreira²

2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) (Cat. No.03CH37490)

View full text Add to dashboard Cite

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

customersupport@researchsolutions.com

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

This site is protected by reCAPTCHA and the Google Privacy Policy and Terms of Service apply.

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

FIR filter implementation using bit-serial arithmetic and partial summation trees

Cited by 2 publications

References 0 publications

The Multiplier Tree FIR filter architecture

The Multiplier Tree FIR filter architecture

The design of low-cost fixed-point FIR digital filters using an improved local search

Contact Info

Product

Resources

About