First demonstration of 40-nm channel length top-gate WS<sub>2</sub> pFET using channel area-selective CVD growth directly on SiO<sub>x</sub>/Si substrate

Cheng, Chuan; Chung, Ying Chien; Li, Uing-Yang; Lin, Chih-Chia; Li, Chi-Feng; Chen, Jyun-Hong; Lai, Tung-Yen; Li, Kai-Shin; Shieh, Jia-Min; Su, Sheng-Kai; Chiang, Hung-Li; Chen, Tzu-Chiang; Li, Lain‐Jong; Wong, H.-S. Philip; Chien, Chao–Hsin

doi:10.23919/vlsit.2019.8776498

Cited by 34 publications

(18 citation statements)

References 7 publications

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“…Despite these features, the electrical properties of edge contacts remain widely unexplored. Demonstrations of edge contacts [37][38][39][40][41][42][43][44] are still in their infancy, in terms of achieving acceptable contact resistances. Edge contacts to TMDs are typically fabricated in the same manner as that of edge contacts to graphene [45], which is achieved by utilizing h-BN encapsulation to isolate the semiconductor surface from the metal contact.…”

Section: -2mentioning

confidence: 99%

One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2 /Metal Interfaces

et al. 2021

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This paper is a contribution to the joint Physical Review Applied and Physical Review Materials collection titled Two-Dimensional Materials and Devices.One-dimensional (1D) edge contacts to two-dimensional (2D) transition-metal dichalcogenides (TMDs), which offer unique features in the design of electronic devices, have recently gained attention. However, the physics of the Schottky barrier of the edge contacts and how exactly it differs from conventional top contacts is not well known. This paper presents a comprehensive ab initio densityfunctional-theory nonequilibrium green's function study of the electrical properties of edge contacts to 2D MoS 2 . It is observed that, due to the intrinsic terminated edge states, 1D edge contacts to MoS 2 are pinned more strongly to a charge-neutrality level that lies closer to the valence band and yields p-type characteristics, which are in contrast to top contacts. This Schottky-barrier anisotropy allows edge contacts in MoS 2 to outperform top contacts in p-type conduction, despite their atomically thin one-dimensional interfaces. Furthermore, the lower limits of contact resistance achievable by edge contacts to MoS 2 are estimated. The role of doping, different edge terminations, and Schottky-barrier inhomogeneity in imperfect edge or hybrid contacts are analyzed to assess and provide design guidelines and conditions under which we can utilize edge contacts for various applications including complimentary field-effect transistor (FET) operation.

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Section: -2mentioning

confidence: 99%

One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2 /Metal Interfaces

et al. 2021

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“…We present a benchmark chart (Fig 5d) to compare the performance of our devices against flake and CVD 2D material FETs in literature 34,35,36,37,38,39,40,41,42,43 . We choose the peak of transconductance (gm,max) measured at VDS = 1 V and SSmin as the two metrics for comparison, similar to conventional Si transistors.…”

Section: Benchmark Projection and Conclusionmentioning

confidence: 99%

Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors

Arutchelvan¹,

Smets²,

Verreck³

et al. 2021

Preprint

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Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with Silicon gate-all-around devices.

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“…Moreover, surface states have limited the performance and reliability in many nano-electronic applications [9,10,11,12,13] whereas the naturally passivated surfaces of vdW materials alleviate the concern of surface states. As a result, TMDs are now actively being considered as channel materials by the semiconductor industry [14,15]. High mobilities are reported [3,16], doping techniques [17,18] are under development, metal-oxide-semiconductor field-effect transistors (MOSFETs) are being fabricated [19,20,21], and contact technology is under investigation [22,23].…”

Section: Introductionmentioning

confidence: 99%

Identification of Two-Dimensional Layered Dielectrics from First Principles

Osanloo¹,

Put²,

Saadat³

et al. 2021

Preprint

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Two-dimensional (2D) van der Waals (vdW) materials promise ideal electrostatic control of charge carrier flow in a channel free of surface roughness or defects. To realize this ideal, good vdW dielectrics are needed in addition to the well explored channel materials. We study the dielectric properties of 32 easily exfoliable vdW materials using first principles methods. Specifically, we calculate the static and optical dielectric response of the monolayer and bulk form. In monolayers, we discover a strong out-of-plane response in GeClF (10.99), LaOBr (13.20), LaOCl (55.80) and PbClF (15.17), while the in-plane dielectric response is strong in BiOCl, PbClF, and TlF, ranging from 64.86 to 98.37. To assess their potential as gate dielectrics, we calculate the bandgap and electron affinity, and estimate the leakage current through the dielectric. We discover seven monolayer 2D dielectrics that promise to outperform bulk HfO2: LaOBr, LaOCl, CaHI, SrBrF, SrHBr, SrHI, and TlF with lower leakage currents at a significantly reduced equivalent oxide thickness. Of these, LaOBr and LaOCl are the most promising and our findings motivate the growth and exfoliation of rare-earth oxyhalides for their use as vdW dielectrics on vdW transistor channel materials.

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First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate

Cited by 34 publications

References 7 publications

One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2 /Metal Interfaces

One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2 /Metal Interfaces

Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors

Identification of Two-Dimensional Layered Dielectrics from First Principles

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First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate

Cited by 34 publications

References 7 publications

One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2 /Metal Interfaces

One-Dimensional Edge Contacts to Two-Dimensional Transition-Metal Dichalcogenides: Uncovering the Role of Schottky-Barrier Anisotropy in Charge Transport across MoS2 /Metal Interfaces

Impact of Device Scaling on the Electrical Properties of MoS2&nbsp;Field-effect Transistors

Identification of Two-Dimensional Layered Dielectrics from First Principles

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Product

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First demonstration of 40-nm channel length top-gate WS₂ pFET using channel area-selective CVD growth directly on SiO_x/Si substrate

Impact of Device Scaling on the Electrical Properties of MoS2 Field-effect Transistors