First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

Chang, Shu-Wei; Lu, Tsung-Han; Yang, Cong-Yi; Yeh, Chia-Yu; Huang, Min-Kun; Meng, Ching-Fan; Chen, Po‐Jen; Chang, Tzu-Feng; Chang, Yan-Shiuan; Jhu, Jhe-Wei; Hong, Tzu-Chieh; Ke, Chi-Ting; Yu, Xin-Ren; Lu, Wen-Hsiang; Baig, Mohammed Aftab; Cho, Ta-Chun; Sung, Po-Jung; Su, Chun-Jung; Hsueh, Fu-Kuo; Chen, Bo‐Yuan; Hu, Hsin‐Hui; Wu, Chien-Ting; Lin, Kun‐Lin; Cheng-Yu, William; Lu, Darsen D.; Kao, Kuo-Hsing; Lee, Yao-Jen; Lin, Cheng-Li; Huang, Kun-Ping; Chen, Kun-Ming; Li, Yiming; Samukawa, Seiji; Chao, Tien−Sheng; Huang, Guo–Wei; Wu, Wen−Fa; Lee, Wen−Hsi; Li, Jiun-Yun; Shieh, Jia-Min; Tarng, Jenn‐Hwan; Wang, Yeong-Her; Yeh, Wen–Kuan

doi:10.1109/ted.2021.3138947

Cited by 24 publications

(8 citation statements)

References 23 publications

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“…Our previous study depicts the entire fabrication process in detail [1]. Therefore, we just describe the process briefly in this study.…”

Section: Device Fabrication and Structurementioning

confidence: 99%

“…Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined dual-work-function-gate heterogeneous CFET (DWFG-HCFET) demonstrated in the previous study [1]. In this study, we will discuss DWFG-HCFET architecture in detail.…”

Section: Introductionmentioning

confidence: 99%

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(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Lee¹,

Chang²,

Lee³

et al. 2022

ECS Trans.

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System-on-panel and monolithic 3D integration must be the main trend in the future. Heterogeneous channel materials need to be integrated on a chip for the different requirements. In the previous work, we innovated an advanced process to combine double gate IGZO high-frequency device and dual work function gate heterogeneous IGZO/Si CFET inverter/SRAM on a substrate. However, the heterogeneous CFET architecture is pretty complicated. Subsequently, the channel design, gate structure, and operation mode for both bottom polysilicon and top IGZO transistor are discussed in detail in this study.

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“…Our previous study depicts the entire fabrication process in detail [1]. Therefore, we just describe the process briefly in this study.…”

Section: Device Fabrication and Structurementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Lee¹,

Chang²,

Lee³

et al. 2022

ECS Trans.

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“…While, complementary field-effect transistor (CFET), which is 3D integration at the transistor level, is a technology that vertically stacks n-ch and p-ch FETs to create a CMOS circuit. [1][2][3][4][5][6][7][8] This improves the footprint of the CMOS circuit and shortens the wiring distance between the n-ch and p-ch FETs comprising the CMOS circuit, resulting in a faster circuit.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Suzuki,

Hara

2024

Jpn. J. Appl. Phys.

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Germanium (Ge) has high mobility and is more suitable for low-temperature device processes than silicon (Si); thus, it has attracted attention as an upper-layer transistor for monolithic three-dimensional (M3D) integration. We evaluated in detail the crystalline quality of extremely thin polycrystalline-Ge (poly-Ge) thin films thinner than 15 nm fabricated by metal-induced crystallization using copper (Cu-MIC) at 400 ℃ using micro-Raman scattering, in-plane X-ray diffraction, transmission electron microscopy (TEM), TEM energy dispersive X-ray spectroscopy, and TEM electron diffraction. Additionally, the films were applied to p-ch double-gate (DG) poly-Ge thin-film transistors (TFTs), and their performance was evaluated. As a result, a high Ion/Ioff ratio of 2.8×103 was realized by crystallization at 400 ℃ with a ratio equal to that of crystallization at 500 °C. This study demonstrated the feasibility of Cu-MIC DG poly Ge TFTs for M3D applications.

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“…Much work has been undertaken to circumvent the thermal budget limitation. For instance, nanosecond laser annealing (NLA) [ 6 ] and solid-phase epitaxial regrowth (SPER) [ 7 ] were used to activate S/D as the alternatives to high-temperature spike annealing and low-temperature materials, such as poly-Si [ 8 , 9 ], Ge [ 10 , 11 ], III-V [ 12 , 13 ] and transparent amorphous oxide [ 14 , 15 ] were implemented to replace monocrystalline Si as the channel of top-tier devices. Particularly interesting is the exploration of junctionless MOSFETs as the top-tier devices with the elimination of S/D activation [ 16 , 17 ].…”

Section: Introductionmentioning

confidence: 99%

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

Mao

Gao

et al. 2022

Nanomaterials

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In this work, low-temperature Schottky source/drain (S/D) MOSFETs are investigated as the top-tier devices for 3D sequential integration. Complementary Schottky S/D FinFETs are successfully fabricated with a maximum processing temperature of 500 °C. Through source/drain extension (SDE) engineering, competitive driving capability and switching properties are achieved in comparison to the conventional devices fabricated with a standard high-temperature (≥1000 °C) process flow. Schottky S/D PMOS exhibits an ON-state current (ION) of 76.07 μA/μm and ON-state to OFF-state current ratio (ION/IOFF) of 7 × 105, and those for NMOS are 48.57 μA/μm and 1 × 106. The CMOS inverter shows a voltage gain of 18V/V, a noise margin for high (NMH) of 0.17 V and for low (NML) of 0.43 V, with power consumption less than 0.9 μW at VDD of 0.8 V. Full functionality of CMOS ring oscillators (RO) are further demonstrated.

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First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications

Cited by 24 publications

References 23 publications

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

(Invited, Digital Presentation) Heterogeneous IGZO/Si CFET Monolithic 3D Integration

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Low-Temperature (≤500 °C) Complementary Schottky Source/Drain FinFETs for 3D Sequential Integration

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