First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

Capogreco, E.; Witters, L.; Arimura, Hiroaki; Sebaai, Farid; Porret, Clément; Hikavyy, Andriy; Loo, Roger; Milenin, Alexey; Eneman, G.; Favia, P.; Bender, Hugo; Wostyn, Kurt; Litta, E. Dentoni; Schulze, Andreas; Vrancken, C.; Opdebeeck, A.; Mitard, J.; Langer, Róbert; Holsteyns, Frank; Waldron, Niamh; Barla, K.; Heyn, V. De; Mocuta, D.; Collaert, N.

doi:10.1109/ted.2018.2871595

Cited by 54 publications

(34 citation statements)

References 22 publications

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“…The introduction of high mobility materials such as Si 1− x Ge x for pMOS and III–V for nMOS devices is therefore being considered despite integration difficulties . Advanced pMOS field effect transistors (FET), with compressively strained Si 1− x Ge x channels grown on top of Si 1− y Ge y (with x > y ) strain relaxed buffers (SRBs) and embedded in fin and gate‐all‐around (GAA) architectures, are for instance being actively developed . In these devices, the strain in the channel can be reinforced by the use of suitable source/drain (S/D) stressor layers, i.e., with a lattice parameter larger than that of the SRB.…”

Section: Introductionmentioning

confidence: 99%

“…In the case of Ge pMOS, compressive Ge channels are grown on top of a Ge‐rich Si 1− y Ge y SRB (e.g., y = 0.7), which allows for enhanced channel carriers mobilities and improved electrostatics . Ge:B and Ge 1− z Sn z :B ( z ≈ 1–2%) are then preferred as S/D materials due to process compatibility (limited thermal budget) and appropriate strain .…”

Section: Introductionmentioning

confidence: 99%

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Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices

Porret

Vohra

Nakazaki³

et al. 2019

Physica Status Solidi (a)

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The peculiarities of heavily boron-doped germanium, selectively grown at low temperature by means of a cyclic deposition and etch chemical vapor deposition process, are investigated through the analysis of the structural and electrical material properties. The incorporation of B in Ge can exceed 6 Â 10 20 cm À3 , close to a factor 100 above the solubility limit, without any significant degradation of the Ge:B crystalline quality, although high B-doping induces an unwanted contraction of the Ge lattice. Micro-Hall effect measurements and the multiring circular transmission line method are used to evaluate the active carrier concentrations and resistivities of Ti/Ge:B contacts. Even though the resistivity of asgrown layers saturates for chemical B concentrations approaching 1 Â 10 21 cm À3 and increases beyond that level, a contact resistivity below 3 Â 10 À9 Ω cm 2 is obtained for the highest active doping concentration, showing that a compromise must be found to decrease the total contact resistance. Finally, first principles simulations are used to understand dopant deactivation mechanisms in the Ge:B system. In conclusion, the formation of boron-interstitial clusters is most likely the cause for electrical performance degradation at high doping values.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices

Porret

Vohra

Nakazaki³

et al. 2019

Physica Status Solidi (a)

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“…In order to overcome the wet crystal orientation anisotropy and liquid capillary effect, dry etching is preferred. The dry etch mainly includes SF 6 /CF 4 /H 2 (selectivity Si to Si 0.5 Ge 0.5 is about 10: 1) [212], CF 4 /H 2 /Ar (selectivity Si to Si 0.5 Ge 0.5 is about 30: 1) [25,213] and CF 4 /N 2 /O 2 (selectivity Si to Si 0.5 Ge 0.5 is about 10: 1) [214]. Both dry and wet etching methods overcome the crystal anisotropy issue, but the etching selection ratio still needs to be improved.…”

Section: High Selective Etching For Channel Full Releasementioning

confidence: 99%

“…Intensive studies for hGAAFETs have been done by several research groups [13,15,[19][20][21][22]24,25]. The first hGAAFET was presented by Colinge et al [19].…”

Section: Introductionmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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“…With this example, we demonstrate the adequacy of the NDS methodology for predicting critical device performance. Ge-channel p-type NWFETs have been demonstrated recently [24], with gate lengths as low as 30 nm. The lower hole effective mass in Ge increases the hole velocity and thus the on-current.…”

Section: B Leakage In Ge-channel P-nwfetsmentioning

confidence: 99%

Nano Device Simulator—A Practical Subband-BTE Solver for Path-Finding and DTCO

Stanojević¹,

Tsai²,

Strof³

et al. 2021

IEEE Trans. Electron Devices

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We present an in-depth discussion on the subband Boltzmann transport (SBTE) methodology, its evolution, and its application to the simulation of nanoscale MOSFETs. The evolution of the method is presented from the point of view of developing a commercial generalpurpose SBTE solver, the GTS nano device simulator (NDS). We show a wide range of applications SBTE is suited for, including state-of-the-art nonplanar and well-established planar technologies. It is demonstrated how SBTE can be employed both as a path-finding tool and a fundamental component in a DTCO-flow.

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First Demonstration of Vertically Stacked Gate-All-Around Highly Strained Germanium Nanowire pFETs

Cited by 54 publications

References 22 publications

Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices

Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices

State of the Art and Future Perspectives in Advanced CMOS Technology

Nano Device Simulator—A Practical Subband-BTE Solver for Path-Finding and DTCO

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