First Experimental Demonstration of Nonbinary LDPC-Coded Modulation Suitable for High-Speed Optical Communications

Fu, Jiaojiao; Arabaci, Murat; Djordjević, Ivan B.; Zhang, Yequn; Xu, Lei; Wang, Ting

doi:10.1364/ofc.2011.owf4

Cited by 5 publications

(4 citation statements)

References 7 publications

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“…Our studies revealed that the proposed nonbinary LDPC-coded modulation (NB-LDPC-CM) schemes can provide higher net coding gains and reduce latency and computational complexity at receivers compared to its binary LDPC-coded modulation counterparts. We also demonstrated the feasibility of the proposed NB-LDPC-CM scheme experimentally in [5].…”

Section: Introductionmentioning

confidence: 91%

Experimental evaluation of high-speed optical fiber communication using nonbinary LDPC coded modulation with layered decoding

Arabaci

Djordjević

2011

2011 13th International Conference on Transparent Optical Networks

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In this paper, we present a reduced-latency nonbinary low-density parity-check (LDPC) coded modulation scheme suitable for high-speed optical fiber communication featuring the layered LDPC decoding algorithm. The use of the layered decoder in place of the conventional flooding decoder helps reduce by half the number of iterations taken in decoding. This in turn reduces the decoding latency, increases the decoding throughput, and significantly lowers the power consumption at the receiving ends of optical transport networks. We show by using the experimental data collected from a 4-ary rate-0.8 LDPC-coded NRZ-DQPSK modulation system that layered decoding indeed halves the required number of decoding iterations. We also show that, in the back-toback configuration, even with a single iteration of layered decoding, one can attain a 7 dB gain in performance at the bit error ratio (BER) of 10 -5 when compared to using only the maximum a posteriori probability detector output based on the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm.

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Section: Introductionmentioning

confidence: 91%

Experimental evaluation of high-speed optical fiber communication using nonbinary LDPC coded modulation with layered decoding

Arabaci

Djordjević

2011

2011 13th International Conference on Transparent Optical Networks

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“…These codes emerge as an alternative to their binary counterparts to overcome the weaknesses shown by binary LDPC codes. Additionally, they improve the burst error correction capability, especially with high order Galois fields, and offer the possibility to be used in conjunction with high-order modulation schemes (16QAM, 64QAM, 256QAM), reducing the complexity in both the encoder and the decoder [5,6]. Unfortunately, NB-LDPC codes have some drawbacks: i) high complexity of their check-node (CN); ii) large amount of area spent on storage elements (RAM memories and registers); and iii) routing congestion that limits the overall decoding throughput.…”

mentioning

confidence: 99%

High-Performance NB-LDPC Decoder With Reduction of Message Exchange

Lacruz

García-Herrero

Canet

et al. 2016

IEEE Trans. VLSI Syst.

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“…These codes perform better than their binary counterparts for codes with low and medium codeword length. Additionally, they improve the burst error-correction capability and work in conjunction with high-order modulation schemes (16QAM, 64QAM, 256QAM) [7,8]. Nowadays, NB-LDPC codes have been considered strong candidates to be used in the 100Gbps optical transport system [9,10].…”

Section: Prefacementioning

confidence: 99%

“…These codes emerge as an alternative to their binary counterparts to overcome the weaknesses shown by binary LDPC codes. Additionally, they improve the burst error correction capability, especially with high order Galois fields, and offer the possibility to be used in conjunction with high-order modulation schemes (16QAM, 64QAM, 256QAM), reducing the complexity in both the encoder and the decoder [7,8]. Unfortunately, NB-LDPC codes have some drawbacks: i) high complexity of their check-node (CN); ii) large amount of area spent on storage elements (RAM memories and registers); and iii) routing congestion that limits the overall decoding throughput.…”

Section: Introductionmentioning

confidence: 99%

VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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This thesis studies the design of low-complexity soft-decision Non-Binary LowDensity Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps).In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended MinSum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput.Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm 2 . The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million iii NAND gates) is increased in almost five times compared to other proposals from literature.The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF (64) ResumenEn esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps).En la primera parte de la tesis los principales aspectos concernientes a los códi-gos NB-LDPC s...

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First Experimental Demonstration of Nonbinary LDPC-Coded Modulation Suitable for High-Speed Optical Communications

Cited by 5 publications

References 7 publications

Experimental evaluation of high-speed optical fiber communication using nonbinary LDPC coded modulation with layered decoding

Experimental evaluation of high-speed optical fiber communication using nonbinary LDPC coded modulation with layered decoding

High-Performance NB-LDPC Decoder With Reduction of Message Exchange

VLSI algorithms and architectures for non-binary-LDPC decoding

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