First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

Abstract

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV /I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent I ON /I OFF characteristics (NMOS: 2.33 mA/μm at 27 pA/μm and PMOS: 1.52 mA/μm at 38 pA/μm). A gate capacitance C gg reduction of 32% is measured, thanks to S-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain A VI (= g m /g ds ) is improved by 92%.Index Terms-A VI , C gg , CV /I, high performances, internal spacers, low standby power, multichannel CMOSFETs (MCFETs), 3-D.

Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains

“…Those stacked Si nanowires were fabricated by (i) growing SiGe/Si superlattices on SOI wafers, (ii) protecting those stacks with a hard mask (in the channel regions), (iii) etching those stacks down to the starting Si film of the SOI substrate in the S/D regions, (iv) laterally etching recesses in the SiGe layers of the resulting fin-like structures, (v) filling those recesses with SiN internal spacers prior to (vi) Si:P SEG. 22 Later in the process flow, the SiGe layers were etched selectively versus Si and the resulting voids filled with the conformal gate stack materials. The surface of these RSDs was smooth, and full selectivity versus SiO 2 (Buried OXyde) and SiN internal spacers was achieved, as illustrated by the Scanning Electron Microscopy images in Figure 5.…”

Gate-all-around technology: Taking advantage of ballistic transport?

“…Making the approximation e spacer = e high-K and L spacer = T ox in GAA, we found that C epi is roughly 40Â higher in GAA than in single gate FDSOI. Nevertheless, Bernard et al [36] proposes the introduction of internal spacers to decouple the gate and the S/D. Fig.…”

“…Slight improvement is found by switching from GAA-bulk integration to GAA-SOI integration thanks to its lower junction capacitance. More interesting, the integration of internal spacers [36] allows the reduction of the coupling between the epitaxially raised S/D and the gate. C epi is thus almost the same for the GAA than for the FDSOI.…”

3D Suspended Nanowires Integration for CMOS and Beyond

“…Moreover, some parasitic capacitances are created by the 3D configuration of such GAA architectures. In (6), a strategy to reduce the parasitic capacitances was proposed. It consisted in introducing internal spacers between the gates and the source/drain before the source/drain epitaxy.…”

“…Nevertheless, aggressive sub-lithographic nanowires' diameters will limit the current drivability of such devices. 3 dimensional (3D) stacked channel architectures were thus proposed (4)(5)(6)(7)(8)(9), with a significant gain in current density per surface area.…”