Gate-all-around technology: Taking advantage of ballistic transport?

Huguenin, J.-L.; Bidal, G.; Denorme, S.; Fleury, Dominique; Loubet, N.; Pouydebasque, A.; Perreau, P.; Leverd, F.; Barnola, S.; Beneyton, R.; Orlando, B.; Gouraud, P.; Salvetat, T.; Clement, L.; Monfray, S.; Ghibaudo, G.; Bœuf, F.; Skotnicki, T.

doi:10.1016/j.sse.2010.04.029

Cited by 18 publications

(3 citation statements)

References 28 publications

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“…In recent technological trends, it is necessary to continuously reduce the dimensions of the device to satisfy Moore's law [4]. The continuing downsizing of the traditional MOSFETSs has demonstrated better performance in various DC/RF parameters [5].…”

Section: Related Workmentioning

confidence: 99%

Design and Development of Biosensors Based on Nano Tube Tunnel Field Effect Transistor

B M Alsalman,

Alsaleh

2023

IJASRE

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Tunnel Field Effect Transistor (TFET) is gaining recognition and provide solution for Integrated Circuit (IC) design with low power. This is due to TFET's carrier transportation scheme, which utilizes inter-band tunneling of carriers, and its fabrication similarity to MOSFET. TFET presents itself as a widely adopted device structure that can overcome the limitations of MOSFETs. However, TFETs suffer from poor DC and Radio Frequency (RF) performance, mainlydue to minority carrier transport and physical doping, which forms an abrupt junction in nanoscale devices due to RDFs. The junction-less device structure presents a viable solution to these issues without sacrificing DC parameters, even at high-frequency. Furthermore, the nanotube structure of TFET effectively reduces the Subthreshold Swing (SS) and leakage current due to better controllability of channel. The gate-all-around structure of nanotube TFET improves the surface potential distribution over the channel region, not only enhancing the DC characteristics of TFET but also improving the high-frequency parameters. The core gate Nano Tube (NT)-TFET is a promising device structure for exploring its application in the field of biomedical science as a biosensor. The proposed core gate nanotube structure provides a larger surface area for immobilizing biomolecules in the cavity, thus improving sensitivity analysis. This work proposes the utility of a novel core gate NT-TFET as a biosensor for detecting label-free biomolecules and DNAs. In this design, the detection capability of biosensor is improved, and the detection processes are investigated by high-frequency parameters of the proposed twin cavity dual metal NT-TFET biosensor. This study demonstrates the sensitivity analysis of biosensor based on transit time and device efficiency, which are two critical high-frequency parameters. This approach results in a biosensor with a lower annealing budget, making it more cost-effective and with comparatively highersensitivity

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Section: Related Workmentioning

confidence: 99%

Design and Development of Biosensors Based on Nano Tube Tunnel Field Effect Transistor

B M Alsalman,

Alsaleh

2023

IJASRE

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“…The continuous scaling of transistor demands the evolution of devices in terms of material and device structure. As the scaling of Fin Field-Effect-Transistor (FinFET) has already reached the limit [1]- [3], a transition to gateall-around (GAA) structures have been proposed to further enhance the electrostatic controllability of the gate and to effectively suppress the short channel effects (SCEs) [4]- [6]. Gallium Nitride (GaN), being one of the most promising candidate to replace silicon, is also known for their superior material properties, such as wide bandgap energy, large saturation velocity, and relatively smaller permittivity [7]- [9].…”

Section: Introductionmentioning

confidence: 99%

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

et al. 2021

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The effects of interface charges on the performances of gate-all-around (GAA) GaN vertical nanowire MOSFETs with different geometries have been studied. Geometrical effect on the gate current of vertical GAA GaN nanowire MOSFET has also been analysed for the first time. In the ideal condition, the circular geometry nanowire (CGN) MOSFET exhibits the best performance with subthreshold swing (SS) of 62 mV/dec, drain-induced barrier lowering (DIBL) of 14 mV/V, and ON/OFF current ratio (I ON /I OFF ) of ∼10 8 . The triangular or hexagonal geometry nanowire (TGN or HGN) MOSFET suffer from large gate leakage current due to the field enhancement at sidewall corners. It is also known that interface traps at the sidewall surface of vertical nanowires deteriorate the overall device performance. The HGN MOSFET with m-plane sidewall demonstrates the best performance with SS of 69 mV/dec and DIBL of 13 mV/V, while the TGN MOSFET with a-plane sidewall exhibits the worst performance with SS of 112 mV/dec and DIBL of 101 mV/V.

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“…Desire to continue the scaling of the planar technology is driven by lower costs when compared to nonplanar technology concepts like various multigate transistor architectures or nanowires [3]. The ultimate goal, here, is to achieve the near-to-ballistic carrier transport with a gate length reduction making the channel shorter [4]. This increases not only the drive current but also the switching speed of a transistor which is the decisive figure to reduce power dissipation [3].…”

Section: Introductionmentioning

confidence: 99%

Monte Carlo Study of Ultimate Channel Scaling in Si and In$_{\rm 0.3}$Ga$_{\rm 0.7}$As Bulk MOSFETs

Islam

Benbakhti

Kálna

2011

IEEE Trans. Nanotechnology

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A detailed analysis of nonequilibrium electron transport in n-type Si and In 0 .3 Ga 0 .7 As MOSFETs scaled into ultimate limit of 5-nm gate length is carried out using ensemble Monte Carlo device simulations. The analysis is based on simulations of I D -V G characteristics for a template, 25-nm gate length Si MOSFET compared against previous results from various Monte Carlo device codes, and for an equivalent 25-nm gate length In 0 .3 Ga 0 .7 As MOSFET. The transistors are then laterally scaled from a gate length of 25 nm to 20, 15, 10 and 5 nm monitoring the average electron velocity, energy, and sheet density along the channel at a supply voltage of 1.0 V. A degradation of the injection velocity with the scaling of a gate/channel length is observed. While we have found a decrease in the overall electron velocity profile along the Si channel for gate lengths smaller than 10 nm and a decrease in the injection velocity from a gate length of 20 nm, the increase in the intrinsic drain current in the scaling process is continuous thanks to the increasing velocity at the drain side. However, the velocity in the InGaAs channel MOSFETs increases steadily during the scaling but the increase in the intrinsic drain current is less pronounced. This is the result of a source starvation, due to a low density of states in III-V semiconductors, which cannot provide a large enough electron sheet density in the channel. This effect is partially mitigated by the enhancement of density of states as a proportion of electrons in the source/drain transfers to upper valleys with a larger electron effective mass.

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Gate-all-around technology: Taking advantage of ballistic transport?

Cited by 18 publications

References 28 publications

Design and Development of Biosensors Based on Nano Tube Tunnel Field Effect Transistor

Design and Development of Biosensors Based on Nano Tube Tunnel Field Effect Transistor

A Simulation Study on the Effects of Interface Charges and Geometry on Vertical GAA GaN Nanowire MOSFET for Low-Power Application

Monte Carlo Study of Ultimate Channel Scaling in Si and In$_{\rm 0.3}$Ga$_{\rm 0.7}$As Bulk MOSFETs

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