2022
DOI: 10.1088/1748-0221/17/03/c03022
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First measurements on the Timespot1 ASIC: a fast-timing, high-rate pixel-matrix front-end

Abstract: This work presents the first measurements performed on the Timespot1 ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32 × 32 channels hybrid-pixel matrix. Targeted to space-time tracking applications in High Energy Physics experiments, the system aims to achieve a time resolution of 30 ps or better at a maximum event rate of 3 MHz/channel with a data driven interface. Power consumption can be programmed to range between 1.2 W/cm2 and 2.6 W/cm2. The presented results includ… Show more

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Cited by 11 publications
(6 citation statements)
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“…Two candidates have been chosen to be the potential predecessor for the VeloPix II used in Upgrade II. The Timespot ASIC offers a time resolution of 30 ps [8], while having a power budget of W/cm 2 . It is designed especially for 3D sensors.…”
Section: Sensor and Asic Considerationsmentioning
confidence: 99%
“…Two candidates have been chosen to be the potential predecessor for the VeloPix II used in Upgrade II. The Timespot ASIC offers a time resolution of 30 ps [8], while having a power budget of W/cm 2 . It is designed especially for 3D sensors.…”
Section: Sensor and Asic Considerationsmentioning
confidence: 99%
“…Dedicated integrated CMOS 28 nm read-out electronics is under development. A small prototype ASIC, named Timespot1, featuring a matrix of 1024 pixels and integrating one TDC per pixel channel has been recently tested being capable of a time resolution around 30 ps on the full read-out chain [59].…”
Section: D Silicon Sensorsmentioning
confidence: 99%
“…The chip is being fabricated with TSMC's 65nm technology using design principles consistent with radiation hardening and targets the following features: picosecond-level timing resolution; 10 Gs/s waveform digitization rate to allow pulse shape discrimination; moderate data buffering (256 samples/chnl); autonomous chip triggering, readout control, calibration and storage virtualization; on-chip feature extraction and multi-channel data fusion; reduced cost and increased reliability due to embedded controller (reduction of external logic). Existing readout approaches, such as ALTIROC [34] and the newer TimeSPOT1 [35], promise good-to-excellent timing resolution and channel density, and use a TDC-based measurement for signal arrival times and time-over-threshold (ToT) for an indirect estimate of integrated charge. However, these readout strategies will likely adversely impact the ability to provide sub-pixel spatial resolution and typically have difficulty compensating for environmental factors such as pile-up, sensor aging, and radiation; timing precision can also be adversely impacted by factors such as timewalk, baseline wander and waveform shape variations.…”
Section: A2 Full Digitization Chipmentioning
confidence: 99%