We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a 32 × 32 pixel matrix with a pitch of 35 μm. Timespot1 is the first small-size prototype, conceived to readout fine-pitch pixels with single-hit time resolution below 50 psrms and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC includes a charge amplifier, a discriminator, and a Time-to-Digital Converter with a time resolution indicatively of 22.6 psrms and maximum readout rates (per pixel) of 3 MHz. To respect system-level constraints, the timing performance has been obtained keeping the power budget per pixel below 40 mW. The ASIC has been tested and characterised in the laboratory concerning its performance in terms of time resolution, power budget and sustainable rates. The ASIC will be hybridized on a matched 32 × 32 pixel sensor matrix and will be tested under laser beam and Minimum Ionizing Particles in the laboratory and at test beams. In this paper we present a description of the ASIC operation and the first results obtained from characterization tests concerning its performance.

This work presents the first measurements performed on the Timespot1 ASIC. As the second prototype developed for the TimeSPOT project, the ASIC features a 32 × 32 channels hybrid-pixel matrix. Targeted to space-time tracking applications in High Energy Physics experiments, the system aims to achieve a time resolution of 30 ps or better at a maximum event rate of 3 MHz/channel with a data driven interface. Power consumption can be programmed to range between 1.2 W/cm2 and 2.6 W/cm2. The presented results include a description of the ASIC operation and a first characterization of its performance in terms of time resolution.

A front-end ASIC for 4D tracking is presented. The prototype includes the block necessary to build a pixel front-end chain for timing measurement, as independent circuits. The architecture includes a charge-sensitive amplifier, a discriminator with programmable threshold, and a timeto-digital converter. The blocks were designed with target specifications in mind including: an area occupation of 55 µm × 55 µm, a power consumption tens of micro ampere per channel and timing a resolution of at least 100 ps. The prototype has been designed and integrated in 28 nm CMOS technology. The presented design is part of the TimeSpOT project which aims to reach a high-resolution particle tracking both in space and in time, in order to provide front-end circuitry suitable for next generation colliders.

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