First measurements with the CMS DAQ and Timing Hub prototype-1

Hegeman, J.; Blazek, R. H.; Behrens, U.; Branson, J. G.; Brummer, Philipp; Cittolin, S.; Silva-Gomes, Diego Da; Darle, Georgiana-Lavinia; Deldicque, Christian; Dobson, M.; Doualot, Nicolas; Fulcher, J.; Gigi, D.; Gladki, Maciej; Glege, F.; Gómez-Ceballos, G.; Hansen, M.; Jevtic, Dragana; Li, Wei; Mecionis, Audrius; Meijers, F.; Mommsen, R. K.; Mor, Keyshav; Morovic, S.; O’Dell, V.; Orsini, L.; Papakrivopoulos, I.; Paus, C.; Petrucci, Andrea; Pieri, M.; Rabady, D.; Raychino, Kolyo; Rácz, A.; Rodriguez-Garcia, Alvaro; Sakulin, H.; Schwick, C.; Šimelevičius, Dainius; Soursos, Panagiotis; Stahl, A.; Stankevičius, Mantas; Suthakar, Uthayanath; Troska, J.; Vazquez-Velez, Cristina; Zahid, A; Zejdl, Petr

doi:10.22323/1.370.0111

Cited by 7 publications

(6 citation statements)

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“…P1V1 [2], a second version, the P1V2, was developed, which fixed a few design mistakes and improved the layout surrounding the various jitter cleaners on the board in order to further reduce phase noise. Both the P1V1 and -V2 satisfy the requirements for clock distribution of the Phase-2 CMS detectors.…”

Section: The Dth Prototyping and Development Processmentioning

confidence: 99%

“…On the D2S side, the aggregated data are read from the HBM, mapped to TCP/IP streams, and transmitted to the D2S network using the built-in 100GbE transceivers. 2 In order to reduce resource usage, the mapping of data sources to Ethernet streams is limited to five predetermined configurations, instead of a fully configurable routing implementation. This design purposely passes all data through the buffer memory, effectively decoupling throughput fluctuations between the input and output sides, in order to avoid switching between explicit 'read-out' and 'buffer' modes.…”

Section: Jinst 17 C05003mentioning

confidence: 99%

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CMS phase-2 DAQ and timing hub prototyping results and perspectives

et al. 2022

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This paper describes recent progress on the design of the DAQ and Timing Hub, or DTH, an ATCA (Advanced Telecommunications Computing Architecture) hub board intended for the phase-2 upgrade of the CMS experiment. Prototyping was originally divided into multiple feature lines, spanning all different aspects of the DTH functionality. The second DTH prototype merges all R&D and prototyping lines into a single board, which is intended to be the production candidate. Emphasis is on the process and experience in going from the first to the second DTH prototype, which included a change of the chosen FPGA as well as the integration of a commercial networking solution.

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Section: The Dth Prototyping and Development Processmentioning

confidence: 99%

Section: Jinst 17 C05003mentioning

confidence: 99%

CMS phase-2 DAQ and timing hub prototyping results and perspectives

et al. 2022

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“…The short-term stability is mainly ensured by this last hop of the network (back-end FPGA, jitter cleaning PLL, and lpGBT). Previous studies have shown that the short-term stability specifications can be comfortably met with such a solution [7].…”

Section: Introductionmentioning

confidence: 99%

TCLink: A Fully Integrated Open Core for Timing Compensation in FPGA-Based High-Speed Links

Mendes

Baron

Hegeman

et al. 2023

IEEE Trans. Nucl. Sci.

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The high luminosity expected in the second phase of the upgrades of the Large Hadron Collider (LHC phase-2 upgrades) will pose unprecedented challenges to its four experiments in terms of collisions density -also known as pileup -per beam crossing. Disentangling the vertices of 200 simultaneous collisions every 25 ns requires high granularity in the detectors, as well as extremely precise and stable timing. While short-term timing stability is usually a concern addressed in timing distribution systems, long-term variations due to changing environmental conditions can accumulate through distribution chains and can dominate the overall timing stability of the systems they serve.Timing distribution systems in LHC experiments typically use high-speed links and clock recovery. This paper presents a logic core that can be used to mitigate long-term temperature variations in high-speed links. The Timing Compensated Link (TCLink) is an open-source firmware core fully integrated in Xilinx Ultrascale Field Programmable Gate Arrays (FPGAs). It demonstrates picosecond-level phase precision over timing distribution systems, improving the overall timing stability in physics experiments.

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“…The use of electronic boards compliant to the PICMG Advanced Telecommunication Computing Architecture (ATCA) standard [1] is being pursued in a number of development projects targeting the upgrades of the Large Hadron Collider (LHC) experiments [2]. Examples of ATCA boards designed for use in future upgrades of LHC experiments are the Apollo [3], Serenity [4], Pulsar-IIb [6,7] and CMS DAQ and Timing Hub [5] boards. In the context of the ATCA standard Hardware Platform Management (HPM) infrastructure, the management of each Field Replaceable Unit (FRU), such as an electronic board, is delegated to an on-board Intelligent Platform Management Controller (IPMC), which can be installed as a permanent part of the board or as an add-on mezzanine to coordinate the FRU operation with the Shelf Manager Controller (ShMC).…”

Section: Introductionmentioning

confidence: 99%

A flexible and low-cost open-source IPMC mezzanine for ATCA boards based on OpenIPMC

et al. 2022

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This work presents the development of an Intelligent Platform Management Controller mezzanine in a Mini DIMM form factor for use in electronic boards compliant to the PICMG Advanced Telecommunication Computing Architecture (ATCA) standard. The module is based on an STMicroelectronics STM32H745 microcontroller running the OpenIPMC open-source software. The mezzanine has been successfully tested on a variety of ATCA boards being proposed for the upgrade of the experiments at the HL-LHC, with its design and firmware being distributed under open-source hardware license.

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First measurements with the CMS DAQ and Timing Hub prototype-1

Cited by 7 publications

References 0 publications

CMS phase-2 DAQ and timing hub prototyping results and perspectives

CMS phase-2 DAQ and timing hub prototyping results and perspectives

TCLink: A Fully Integrated Open Core for Timing Compensation in FPGA-Based High-Speed Links

A flexible and low-cost open-source IPMC mezzanine for ATCA boards based on OpenIPMC

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